MT47H16M16BG-3ITB Datasheet, PDF (5/129 Pages) Micron Technology – 256Mb: x4, x8, x16 DDR2 SDRAM

256Mb: x4, x8, x16 DDR2 SDRAM
Features
List of Figures
Figure 1: 256Mb DDR2 Part Numbers ............................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................... 8
Figure 3: 64 Meg x 4 Functional Block Diagram ............................................................................................... 11
Figure 4: 32 Meg x 8 Functional Block Diagram ............................................................................................... 12
Figure 5: 16 Meg x 16 Functional Block Diagram ............................................................................................. 13
Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 14
Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) ............................................................................... 15
Figure 8: 84-Ball, FBGA Package (8mm x 14mm) – x16 ..................................................................................... 18
Figure 9: 60-Ball, FBGA Package (8mm x 12mm) – x4, x8 ................................................................................. 19
Figure 10: Example Temperature Test Point Location ...................................................................................... 22
Figure 11: Single-Ended Input Signal Levels ................................................................................................... 41
Figure 12: Differential Input Signal Levels ...................................................................................................... 42
Figure 13: Differential Output Signal Levels .................................................................................................... 44
Figure 14: Output Slew Rate Load .................................................................................................................. 45
Figure 15: Full Strength Pull-Down Characteristics ......................................................................................... 46
Figure 16: Full Strength Pull-Up Characteristics .............................................................................................. 47
Figure 17: Reduced Strength Pull-Down Characteristics .................................................................................. 48
Figure 18: Reduced Strength Pull-Up Characteristics ...................................................................................... 49
Figure 19: Input Clamp Characteristics .......................................................................................................... 50
Figure 20: Overshoot ..................................................................................................................................... 51
Figure 21: Undershoot ................................................................................................................................... 51
Figure 22: Nominal Slew Rate for ^tIS ............................................................................................................... 56
Figure 23: Tangent Line for ^tIS ........................................................................................................................ 56
Figure 24: Nominal Slew Rate for ^tIH .............................................................................................................. 57
Figure 25: Tangent Line for ^tIH ....................................................................................................................... 57
Figure 26: Nominal Slew Rate for ^tDS ............................................................................................................. 62
Figure 27: Tangent Line for ^tDS ...................................................................................................................... 62
Figure 28: Nominal Slew Rate for ^tDH ............................................................................................................. 63
Figure 29: Tangent Line for ^tDH ..................................................................................................................... 63
Figure 30: AC Input Test Signal Waveform Command/Address Balls ................................................................ 64
Figure 31: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ............................................ 64
Figure 32: AC Input Test Signal Waveform for Data with DQS (Single-Ended) ................................................... 65
Figure 33: AC Input Test Signal Waveform (Differential) .................................................................................. 65
Figure 34: MR Definition ............................................................................................................................... 73
Figure 35: CL ................................................................................................................................................. 76
Figure 36: EMR Definition ............................................................................................................................. 77
Figure 37: READ Latency ............................................................................................................................... 80
Figure 38: WRITE Latency .............................................................................................................................. 80
Figure 39: EMR2 Definition ........................................................................................................................... 81
Figure 40: EMR3 Definition ........................................................................................................................... 82
Figure 41: DDR2 Power-Up and Initialization ................................................................................................. 83
Figure 42: Example: Meeting ^tRRD (MIN) and ^tRCD (MIN) .............................................................................. 86
Figure 43: Multibank Activate Restriction ....................................................................................................... 87
Figure 44: READ Latency ............................................................................................................................... 89
Figure 45: Consecutive READ Bursts .............................................................................................................. 90
Figure 46: Nonconsecutive READ Bursts ........................................................................................................ 91
Figure 47: READ Interrupted by READ ............................................................................................................ 92
Figure 48: READ-to-WRITE ............................................................................................................................ 92
Figure 49: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 93
Figure 50: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 93
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. N 7/11 EN
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