M25PX16SOVZM6TP Datasheet, PDF (34/65 Pages) Micron Technology – 16-Mbit, dual I/O, 4-Kbyte subsector erase, serial Flash memory with 75 MHz SPI bus interface

Instructions
M25PX16
instruction issued while an Erase, Program or Write cycle is in progress, is rejected without
having any effect on the cycle that is in progress.
Figure 17. Read OTP (ROTP) instruction and data-out sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction
24-bit address
DQ0
DQ1
High Impedance
23 22 21 3 2 1 0
6.11
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy byte
DQ0
DQ1
76543210
DATA OUT 1
76543210
MSB
DATA OUT n
765432107
MSB
MSB
AI13573
1. A23 to A7 are Don't care.
2. 1 ≤ n ≤ 65.
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address bytes and at least one data byte on Serial Data input
(DQ0). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that
goes beyond the end of the current page are programmed from the start address of the
same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip
Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 18.
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