MT28C3212P2FL Datasheet, PDF (33/47 Pages) Micron Technology – FLASH AND SRAM COMBO MEMORY

2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
FLASH READ CYCLE TIMING REQUIREMENT
VCC = 1.65V–1.95V
PARAMETER
Address to output delay
CE# LOW to output delay
Page address access
OE# LOW to output delay
F_RP# HIGH to output delay
F_RP# LOW pulse width
CE# or OE# HIGH to output High-Z
Output hold from address, CE# or OE# change
READ cycle time
SYMBOL
t_AA
t_ACE
t_APA
t_AOE
t_RWH
t_RP
t_OD
t_OH
t_RC
-10
VCC = 1.65V–1.95V
MIN
MAX
100
100
35
30
200
125
25
0
100
-11
VCC = 1.65V–1.95V
MIN
MAX
110
110
45
30
200
125
25
0
110
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
FLASH READ CYCLE TIMING REQUIREMENT
VCC = 1.80V–2.20V
PARAMETER
Address to output delay
CE# LOW to output delay
Page address access
OE# LOW to output delay
F_RP# HIGH to output delay
F_RP# LOW pulse width
CE# or OE# HIGH to output High-Z
Output hold from address, CE# or OE# change
READ cycle time
SYMBOL
t_AA
t_ACE
t_APA
t_AOE
t_RWH
t_RP
t_OD
t_OH
t_RC
-10
VCC = 1.80V–2.20V
MIN
MAX
95
95
35
30
150
100
25
0
95
-11
VCC = 1.80V–2.20V
MIN
MAX
100
100
45
30
150
100
25
0
100
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
33
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©2002, Micron Technology, Inc.