MT28C3212P2FL Datasheet, PDF (1/47 Pages) Micron Technology – FLASH AND SRAM COMBO MEMORY

FLASH AND SRAM
COMBO MEMORY
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
MT28C3212P2FL
MT28C3212P2NFL
Low Voltage, Extended Temperature
FEATURES
• Flexible dual-bank architecture
• Support for true concurrent operations with no
latency:
Read bank b during program bank a and vice versa
Read bank b during erase bank a and vice versa
• Organization: 2,048K x 16 (Flash)
128K x 16 (SRAM)
• Basic configuration:
Flash
Bank a (4Mb Flash for data storage)
– Eight 4K-word parameter blocks
– Seven 32K-word blocks
Bank b (28Mb Flash for program storage)
– Fifty-six 32K-word main blocks
SRAM
2Mb SRAM for data storage
– 128K-words
• F_VCC, VCCQ, F_VPP, S_VCC voltages¹
1.65V (MIN)/1.95V (MAX) F_VCC read voltage or
1.80V (MIN)/2.20V (MAX) F_VCC read voltage
1.65V (MIN)/1.95V (MAX) S_VCC read voltage or
1.80V (MIN)/2.20V (MAX) S_VCC read voltage
1.65V (MIN)/1.95V (MAX) VCCQ or
1.80V (MIN)/2.20V (MAX) VCCQ
1.80V (TYP) F_VPP (in-system PROGRAM/ERASE)
0.0V (MIN)/2.20V (MAX) F_VPP (in-system
PROGRAM/ERASE)²
12V ±5% (HV) F_VPP (production programming
compatibility)
• Asynchronous access time¹
Flash access time: 100ns or 110ns @ 1.65V F_VCC
SRAM access time: 100ns @ 1.65V S_VCC
• Page Mode read access¹
Interpage read access: 100ns/110ns @ 1.65V F_VCC
Intrapage read access: 35ns/45ns @ 1.65V F_VCC
• Low power consumption
• Enhanced suspend options
ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank
• Read/Write SRAM during program/erase of Flash
• Dual 64-bit chip protection registers for security
purposes
• PROGRAM/ERASE cycles
100,000 WRITE/ERASE cycles per block
BALL ASSIGNMENT
66-Ball FBGA (Top View)
1
2
3
4
5
6
7
8
9 10 11 12
A NC
NC
A20
A11 A15 A14 A13 A12 F_VSS VccQ
NC
NC
B
A16
A8
A10
A9 DQ15 S_WE# DQ14 DQ7
C
F_WE# NC
DQ13 DQ6 DQ4 DQ5
D
S_VSS F_RP#
DQ12 S_CE2 S_VCC F_VCC
E
F_WP# F_VPP A19 DQ11
DQ10 DQ2 DQ3
F
S_LB# S_UB# S_OE#
DQ9 DQ8 DQ0 DQ1
G
A18
A17
A7
A6
A3
A2
A1 S_CE1#
H NC
NC F_VCC A5
A4
A0 F_CE# F_VSS F_OE# NC
NC
NC
Top View
(Ball Down)
• Cross-compatible command set support
Extended command set
Common Flash interface (CFI) compliant
NOTE:
1. These specifications are guaranteed for operation
within either one of two voltage ranges, 1.65V–1.95V
or 1.80V–2.20V. Use only one of the two voltage
ranges for PROGRAM and ERASE operations.
2. MT28C3212P2NFL only.
OPTIONS
MARKING
• Timing
100ns
-10
110ns
-11
• Boot Block
Top
T
Bottom
B
• VPP1 Range
0.9V–2.2V
None
0.0V–2.2V
N
• Operating Temperature Range
Commercial Temperature (0^oC to +70^oC) None
Extended Temperature (-40^oC to +85^oC) ET
• Package
66-ball FBGA (8 x 8 grid)
FL
Part Number Example:
MT28C3212P2FL-10 TET
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
1
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.