MT28S4M16B1LC Datasheet, PDF (30/60 Pages) Micron Technology – SYNCFLASH MEMORY

ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
FLASH MEMORY
FUNCTIONAL DESCRIPTION
The SyncFlash memory incorporates a number of
features that make it ideally suited for code storage
and execute-in-place applications on an SDRAM bus.
The memory array is segmented into individual erase
blocks. Each block may be erased without affecting
data stored in other blocks. These memory blocks are
read, programmed, and erased by issuing commands
to the command execution logic (CEL). The CEL con-
trols the operation of the internal state machine (ISM),
which completely controls all READ DEVICE CONFIGU-
RATION, READ STATUS REGISTER, CLEAR STATUS
REGISTER, RESET DEVICE/CONFIRM, PROGRAM
SETUP/CONFIRM, PROTECT BLOCKS/CONFIRM,
PROTECT DEVICE/CONFIRM, UNPROTECT DEVICE
/CONFIRM, UNPROTECT BLOCKS/CONFIRM, ERASE
NVMODE REGISTER, PROGRAM NVMODE REGISTER,
DISABLE HARDWARE LCR, ERASE SETUP CONFIRM
and CHIP INITIALIZATION operations. The ISM pro-
tects each memory location from overerasure and opti-
mizes each memory location for maximum data reten-
tion. In addition, the ISM greatly simplifies the control
necessary for programming the device in-system or in
an external programmer.
The Flash Memory Functional Description provides
detailed information on the operation of the SyncFlash
memory and is organized into these sections:
• Command Sequences
• Memory Architecture
• Output (READ) Operations
• Input Operations
• Command Execution
• Reset/Power-Down Mode
• Error Handling
• PROGRAM/ERASE Cycle Endurance
FLASH COMMAND SEQUENCES
All Flash operations are performed using either a
hardware command sequence (HCS) or a software com-
mand sequence (SCS). The HCS operations are used in
systems that support the LOAD COMMAND REGIS-
TER (LCR) command. In systems that do not have the
ability to generate an LCR command, SCS operations
can be used for Flash operations. A Flash command
sequence (FCS) is used to describe Flash operations
where the actual implementation (HCS or SCS) is not
relevant.
HARDWARE COMMAND SEQUENCE (HCS)
All HCS operations are executed with LCR, LCR/
ACTIVE/READ, or LCR/ACTIVE/WRITE commands
and command sequences as defined in Truth Tables 1
and 2a. See PROGRAM/ERASE diagram for timing in-
formation. See the SDRAM Interface Functional De-
scription for information on reading the memory array.
Address pins A0–A7 are used to input 8-bit com-
mands during the LCR command cycle. This command
will identify which Flash operation is initiated.
Certain LCR/active/write command sequences re-
quire an 8-bit confirmation code on the WRITE cycle.
The confirmation code is input on DQ0–DQ7.
SOFTWARE COMMAND SEQUENCE (SCS)
Flash operations can also be performed using an
SCS. The SCS uses a series of standard CPU READ and
WRITE op-codes to perform Flash operations. This com-
mand interface is similar to the multistep sequence
common in standard Flash components. Table 3 is an
example of programming data into a particular address
using SCS. See Truth Table 2b for a description of SCS
operations.
Table 3¹
Software Code to Program Data Value 1234h to Address 0000h Using SCS
ASSEMBLY CODE EXECUTED
OP-CODE
ADDRESS, DATA
WRITE
00000055h, 00000000h
WRITE
0000552Ah, 00000055h
WRITE
00008040h, 000000A0h
WRITE
00000000h, 00001234h
SDRAM COMMANDS ISSUED
COMMAND BANK
ADDRESS DATA
ACTIVE
0h
WRITE
0h
000h
55h
XXXX
0000h
ACTIVE
0h
WRITE
0h
055h
2Ah
XXXX
0055h
ACTIVE
0h
WRITE
0h
080h
40h
XXXX
00A0h
ACTIVE
0h
WRITE
0h
000h
00h
XXXX
1234h
NOTE: 1. This is a programming example for the 4 Meg x 16.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev.2 , Pub. 4/02
30
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©2002, Micron Technology, Inc.