MT28S4M16B1LC Datasheet, PDF (17/60 Pages) Micron Technology – SYNCFLASH MEMORY

ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
NOTE: 1. CMD = Command: decoded from CS#, RAS#, CAS#, and WE# inputs.
2. NOP/COMMAND INHIBIT/BURST TERMINATE/ACTIVE TERMINATE commands can be issued throughout the HCS or SCS.
Additionally, LOAD COMMAND REGISTER may be issued throughout the SCS.
3. After a PROGRAM or ERASE operation is registered to the ISM and prior to completion of the ISM operation, a READ to any
location in the bank under ISM control will output the contents of the row activated prior to the LCR/active/write sequence
(see Note 14).
4. To meet the ^tRCD specification, the appropriate number of NOP/COMMAND INHIBIT commands must be issued between
ACTIVE and READ/WRITE commands.
5. The ERASE, PROGRAM, PROTECT, and UNPROTECT operations are self-timed. The status register may be polled to monitor
these operations.
6. x32: A8–A10, x16: A8–A11 are “Don’t Care.”
7. A row will not be opened when ACTIVE is preceded by LCR. ACTIVE is considered a NOP.
8. x32 Data Inputs, DQ8–DQ31 are “Don’t Care” except for DIN, where all DQ31–DQ0 are driven.
x16 Data Inputs, DQ8–DQ15 are "Don’t Care" except for DIN, where all DQ15–DQ0 are driven.
Data Outputs: All unused bits are driven LOW.
9. VHH = 7.0V–8.5V
10. Address must be any row address in the block desired to be protected
11. CAROW, CACOL = Configuration address
This value changes depending on the bit location being accessed
CAROW = X02h for block protect bit, which corresponds to the block row address: x32: X = 0, 2, 4, or 6h
x16: X = 0, 4, 8, or Ch
For all other bits CAROW = XXXh (“Don’t Care”)
CACOL = Values shown below
00h = Manufacturer compatibility ID = 2Ch
01h = Device ID MT28S4M16B1 = D5h
Device ID MT28S2M32B1 = D4h
02h = Block protect bit (BPB)
03h = Device protect bit (DPB)
04h = Mode register
05h = Hardware load command register (LCR) bit
06h/07h = Reserved for future use
12. BA = Bank address must match for all the cycles, except for manufacturer ID/device ID/device protect where it is xxh.
13. The proper command sequence (LCR/active/write) is needed to initiate an ERASE, PROGRAM, PROTECT, or UNPROTECT
operation.
14. If the device protect bit is not set, RP# = VIH unprotects all sixteen ( x32: 128K-Dword, x16: 256K-word ) erasable blocks,
except for blocks 0 and 15. When RP# = VHH, all sixteen ( x32: 128K-Dword, x16: 256K-word) erasable blocks (including
blocks 0 and 15) will be unprotected, and the device protect bit will be ignored. If the device protect bit is set and RP# =
VIH, the block protect bits cannot be modified.
15. If the device protect bit is set, then an ERASE, PROGRAM, PROTECT, or UNPROTECT operation can still be initiated by
bringing RP# to VHH prior to the WRITE command cycle and holding it at VHH until the operation is completed.
16. LBDa = Lock bit data
01h = Set block protect bit
F1h = Set device protect bit
If the DPB is not set, RP# = VIH; all blocks can be set
If the DPB is set, RP# = VIH; BPBs cannot be modified
RP# = VHH; all BPBs can be modified
To set DPB, RP# = VHH is a must
RP# = VHH; all blocks including 0 and 15 are unprotected (reset); DPB does not matter
LBDb = Lock bit data
D0h = Clear block and device protect bits
If the DPB is not set, RP# = VIH; all blocks except 0 and 15 are unprotected (reset)
If the DPB is set, RP# = VIH; block protect bits cannot be modified
RP# = VHH; all blocks including 0, 15, and DPB are unprotected (reset)
17. Bank L: [BA1,BA0] = [0,0] or [0,1]
Bank U: [BA1 BA0] = [1,0] or [1,1]
18. If [BA1, BA0] = [0,0] or [0,1], then WRITE NVMODE REGISTER operation is performed. If [BA1, BA0] = [1,0] or [1,1], then
DISABLE HARDWARE LCR operation is performed.
19. Hardware LCR is preset to “1.” Hardware LCR bit is a one time programmable bit and cannot be reset to “1” after
programmed to “0.”
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
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©2002, Micron Technology, Inc.