MT48LC4M16A2B4-6AITJ Datasheet, PDF (26/83 Pages) Micron Technology – SDR SDRAM

64Mb: x4, x8, x16 SDRAM
Electrical Specifications – AC Operating Conditions
8. ^tAC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design.
9. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge states
(READ, WRITE, including ^tWR, and PRECHARGE commands). CKE may be used to reduce
the data rate.
10. ^tHZ defines the time at which the output achieves the open circuit condition; it is not a
reference to V_OH or V_OL. The last valid data element will meet ^tOH before going High-Z.
11. Parameter guaranteed by design.
12. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-
cesses to a particular row address may result in reduction of the product lifetime.
13. AC characteristics assume ^tT = 1ns.
14. Auto precharge mode only. The precharge timing budget (^tRP) begins at 6ns for -6, at
7ns for -7E, and 7.5ns for -75 after the first clock delay and after the last WRITE is execu-
ted.
15. Precharge mode only.
16. CLK must be toggled a minimum of two times during this period.
17. Required clocks are specified by JEDEC functionality and are not dependent on any tim-
ing parameter.
18. Timing specified by ^tCKS. Clock(s) specified as a reference only at minimum cycle rate.
19. Timing is specified by ^tWR plus ^tRP. Clock(s) specified as a reference only at minimum cy-
cle rate.
20. Based on ^tCK = 7.5ns for -75 and -7E, 6ns for -6.
21. Timing is specified by ^tWR.
22. JEDEC and PC100 specify three clocks.
PDF: 09005aef80725c0b
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN
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