MT9VDDT3272AY Datasheet, PDF (25/27 Pages) Micron Technology – DDR SDRAM UNBUFFERED DIMM

128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 21: Serial Presence-Detect Matrix
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”
BYTE
DESCRIPTION
ENTRY (VERSION) MT9VDDT1672A MT9VDDT3272A MT9VDDT6472A
0 Number of SPD Bytes Used by Micron
128
80
80
80
1 Total Number of Bytes in SPD Device
256
08
08
08
2 Fundamental Memory Type
SDRAM DDR
07
07
07
3 Number of Row Addresses on Assembly
12 or 13
0C
0D
0D
4 Number of Column Addresses on
10 or 11
0A
0A
0B
Assembly
5 Number of Physical Ranks on DIMM
1
01
01
01
6 Module Data Width
72
48
48
48
7 Module Data Width (Continued)
0
00
00
00
8 Module Voltage Interface Levels
SSTL 2.5V
04
04
04
9 _{SDRAM Cycle Time,} ^t_{CK (CAS Latency =}
5ns (-40B)
50
50
50
3)
10 _{SDRAM Access from Clock,} t_{AC (CAS}
0.7ns (-40B)
70
70
70
Latency = 3)
11 Module Configuration Type
ECC
02
02
02
12 Refresh Rate/Type
15.62µs, 7.8µs/SELF
80
82
82
13 SDRAM Device Width (Primary DDR
8
SDRAM)
08
08
08
14 Error-checking DDR SDRAM Data
8
Width
08
08
08
15 Minimum Clock Delay, Back-to-Back
1 clock
01
01
01
Random Column Access
16 Burst Lengths Supported
2, 4, 8
0E
0E
0E
17 Number of Banks on DDR SDRAM
4
Device
04
04
04
18 CAS Latencies Supported
3, 2.5, 2
1C
1C
1C
19 CS Latency
0
01
01
01
20 WE Latency
1
02
02
02
21 SDRAM Module Attributes
Unbuffered/Diff.
20
20
20
Clock
22 SDRAM Device Attributes: General
Fast/Concurrent AP
C0
C0
C0
23 _{SDRAM Cycle Time,} ^t_{CK (CAS Latency =} 6ns (for PC2700
60
60
60
2.5)
system compatibility)
24 _{SDRAM Access from CK,} t_{AC (CAS}
0.7ns (for PC 2700
70
70
70
Latency = 2.5)
system compatibility)
25 _{SDRAM Cycle Time,} t_{CK (CAS Latency =} 7.5ns (for PC 2100
75
75
75
2)
and PC 1600 system
compatibility)
26 _{SDRAM Access from CK,} ^t_{AC (CAS}
0.75ns (for PC 2100
75
75
75
Latency = 2)
and PC 1600 system
compatibility)
27 _{Minimum Row Precharge Time,} t_RP
15ns (-40B)
3C
3C
3C
28 Minimum Row Active to Row Active,
10ns (-40B)
28
28
28
t_RRD
29 _{Minimum RAS# to CAS# Delay,} t_RCD
15ns (-40B)
3C
3C
3C
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
25
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©2004 Micron Technology, Inc.