MT28F016S5 Datasheet, PDF (23/24 Pages) Micron Technology – 2 MEG x 8 SMART 5 EVEN-SECTORED FLASH MEMORY

ADVANCE
2 MEG x 8
SMART 5 EVEN-SECTORED FLASH MEMORY
V_IH
A0-A20
V_IL
V_IH
WE#
V_IL
V_IH
OE#
V_IL
V_IH
CE# _VIL
DQ0-DQ7 ^VIH
V_IL
RY/BY#
RP#
V_OH
V_OL
V_HH
V_IH
V_IL
V_PPH2
V_PPH1
VPP
V_IL
WRITE/ERASE CYCLE
CE#-CONTROLLED WRITE/ERASE
Note 1
tAS
tAH
AIN
tAS
tAH
tWS
tCP
tWH
tWC
tCPH
tWR
tWED1, ₂
tDH
tDH
tDS
tDS
CMD
in
CMD/
Data-in
tWB
tRS
tRYBY
tVPS
[12V VPP]
[5V VPP]
Status
(SR7=0)
WRITE SETUP or
ERASE SETUP
input
WRITE or block
address asserted, and
WRITE data or ERASE
CONFIRM
WRITE or ERASE
executed, status register
checked for completion
TIMING PARAMETERS
SYMBOL
t_WC
t_CPH
t_CP
t_AS
t_AH
t_DS
t_DH
t_WS
t_WH
-9
MIN
90
25
50
40
5
40
5
0
0
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
t_VPS2
t_RS
t_VPH2
t_RYBY
t_WB
t_WED1
t_WED2
t_WR
Status
(SR7=1)
CMD
in
tVPH
Command for next
operation issued
DON’T CARE
-9
MIN
100
1,000
0
90
90
6
600
0
UNITS
ns
ns
ns
ns
ns
µs
ms
ns
NOTE: 1. Address inputs are “Don’t Care” but must be held stable.
2. Measured with VPP = VPPH = 5V.
2 Meg x 8 Smart 5 Even-Sectored Flash Memory
F42.p65 – Rev. 1/00
23
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©2000, Micron Technology, Inc.