MT55L512L18P-1 Datasheet, PDF (22/30 Pages) Micron Technology – 8Mb ZBT SRAM

8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
FBGA THERMAL RESISTANCE
DESCRIPTION
Junction to Ambient
(Airflow of 1m/s)
Junction to Case (Top)
Junction to Pins (Bottom)
CONDITIONS
SYMBOL TYP
Test conditions follow standard test methods
θ_JA
40
and procedures for measuring thermal
impedance, per EIA/JESD51.
θ_JC
9
θ_JB
17
UNITS NOTES
°C/W 1, 11
°C/W 1, 11
°C/W 1, 11
AC ELECTRICAL CHARACTERISTICS
(Notes 2, 3, 4) (0°C ≤ T_A ≤ +70°C; VDD = +3.3V ±0.165V unless otherwise noted)
DESCRIPTION
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Output Times
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Setup Times
Address
Clock enable (CKE#)
Control signals
Data-in
Hold Times
Address
Clock enable (CKE#)
Control signals
Data-in
-6
SYMBOL MIN MAX
-7.5
MIN MAX
t_KHKH
6.0
7.5
f_KF
166
133
t_KHKL
1.7
2.0
t_KLKH
1.7
2.0
t_KHQV
3.5
4.2
t_KHQX
1.5
1.5
t_{KHQX1 1.5}
1.5
t_KHQZ
1.5
3.5
1.5
3.5
t_GLQV
3.5
4.2
t_GLQX
0
0
t_GHQZ
3.5
4.2
t_AVKH
1.5
1.7
t_EVKH
1.5
1.7
t_CVKH
1.5
1.7
t_DVKH
1.5
1.7
t_KHAX
0.5
0.5
t_KHEX
0.5
0.5
t_KHCX
0.5
0.5
t_KHDX
0.5
0.5
-10
MIN MAX UNITS NOTES
10
ns
100 MHz
3.2
ns
5
3.2
ns
5
5.0
ns
1.5
ns
6
1.5
ns 6, 7, 8, 9
1.5
3.5
ns 6, 7, 8, 9
5.0
ns
2
0
ns 6, 7, 8, 9
5.0
ns 6, 7, 8, 9
2.0
ns
10
2.0
ns
10
2.0
ns
10
2.0
ns
10
0.5
ns
10
0.5
ns
10
0.5
ns
10
0.5
ns
10
NOTE: 1. This parameter is sampled.
2. OE# can be considered a “Don’t Care” during WRITEs; however, controlling OE# can help fine-tune a system for
turnaround timing.
3. Test conditions as specified with output loading as shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V ±0.165V) and
Figure 3 for 2.5V I/O (VDDQ = +2.5V +0.4V/-0.125V).
4. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is
defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.
5. Measured as HIGH above VIH and LOW below VIL.
6. Refer to Technical Note TN-55-01, “Designing with ZBT SRAMs,” for a more thorough discussion on these parameters.
7. This parameter is sampled.
8. This parameter is measured with output loading as shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
9. Transition is measured ±200mV from steady state voltage.
10. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when they are being registered into the device. All other synchronous inputs must meet the setup and hold times
with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each
rising edge of CLK when ADV/LD# is LOW to remain enabled.
11. Preliminary package data.
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_2.p65 – Rev. 6/01
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.