MT55L512L18P-1 Datasheet, PDF (2/30 Pages) Micron Technology – 8Mb ZBT SRAM

SA0, SA1, SA
CLK
CKE#
MODE
K
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
FUNCTIONAL BLOCK DIAGRAM
512K x 18
19
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
19
17
19
SA1 _D1
Q1 ^SA1'
SA0 _D0 BURST _Q0 SA0'
LOGIC
ADV/LD#
K
19
WRITE ADDRESS
19
REGISTER 2
ADV/LD#
BWa#
BWb#
R/W#
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
18
O
U
T
S
E
N
P
U
T
WRITE
512K x 9 x 2
18
18
S
E
18
R
E
DRIVERS
MEMORY
A
ARRAY
M
P
S
G
I
S
T
E
R
S
18
O
U
T
D
P
A
U
T
T
A
S
18
B
U
T
F
E
F
E
E
R
R
I
S
N
G
18
DQs
E
E
18
INPUT
18
INPUT
REGISTER 1 E
REGISTER 0 E
OE#
CE#
CE2
CE2#
SA0, SA1, SA
CLK
CKE#
MODE
K
READ LOGIC
FUNCTIONAL BLOCK DIAGRAM
256K x 32/36
18
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
18
16
18
SA1 _D1
Q1 ^SA1'
SA0 _D0 BURST _Q0 SA0'
LOGIC
ADV/LD#
K
18
WRITE ADDRESS
18
REGISTER 2
ADV/LD#
BWa#
BWb#
BWc#
BWd#
R/W#
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
36
WRITE
DRIVERS
O
U
T
256K x 8 x 4
(x32)
36 256K x 9 x 4 36
S
E
N
S
E
36
P
U
T
R
E
36
(x36)
A
M
MEMORY
P
ARRAY
S
G
I
S
T
E
R
S
O
U
T
D
P
A
U
T
T
A
S
36
B
U
T
F
E
F
E
E
R
R
I
S
N
G
36
DQs
DQPa
DQPb
DQPc
DQPd
E
E
INPUT
36
REGISTER 1 E
INPUT
REGISTER 0 E
OE#
CE#
CE2
CE2#
READ LOGIC
NOTE: Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing diagrams
for detailed information.
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_2.p65 – Rev. 6/01
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.