MT28F321P20 Datasheet, PDF (22/35 Pages) Micron Technology – FLASH MEMORY

STANDBY MODE
Icc supply current is reduced by applying a logic
HIGH level on CE# and RST# to enter the standby
mode. In the standby mode, the outputs are placed in
High-Z. Applying a CMOS logic HIGH level on CE# and
RST# reduces the current to ICC3 (MAX). If the device is
deselected during an ERASE operation or during pro-
gramming, the device continues to draw current until
the operation is complete.
AUTOMATIC POWER SAVE MODE (APS)
Substantial power savings are realized during peri-
ods when the array is not being read and the device is in
the active mode. During this time the device switches
to the automatic power save mode. When the device
switches to this mode, ICC is reduced to a level compa-
rable to ICC3. Further power savings can be realized by
applying a logic HIGH level on CE# to place the device
in standby mode. The low level of power is maintained
until another operation is initiated. In this mode, the I/
Os retain the data from the last memory address read
until a new address is read. This mode is entered auto-
matically if no address or control signals toggle.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
DEVICE RESET
To correctly reset the Flash memory devices, the
RST# signal must be asserted (RST# = VIL) for a mini-
mum of ^tRP. After reset, the devices can be accessed for
a READ operation with a delayed access time of ^tRWH
from the rising edge of RST#. The circuitry used for
generating the RST# signal needs to be common with
the rest of the system reset to ensure that correct sys-
tem initialization occurs. Please refer to the timing dia-
gram for further details.
POWER-UP SEQUENCE
The following power-up sequence is recommended
to properly initialize internal chip operations:
• At power-up, RST# should be kept at VIL for 2µs
after VCC reaches VCC (MIN).
• VCCQ should not come up before VCC.
• VPP should be kept at VIL to maximize data
integrity.
When the power-up sequence is completed, RST#
should be brought to VIH. To ensure a proper power-up,
the rise time of RST# (10%–90%) should be <10µs.
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
22
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©2002, Micron Technology, Inc.