MT18VDDF6472DG Datasheet, PDF (22/31 Pages) Micron Technology – DDR SDRAM REGISTERED DIMM

512MB, 1GB (x72, ECC, SR) PC3200
184-PIN DDR SDRAM RDIMM
Table 15: PLL Clock Driver Timing Requirements and Switching Characteristics
Note: 1
PARAMETER
Operating Clock Frequency
Input Duty Cycle
Stabilization Time
Cycle to Cycle Jitter
Static Phase Offset
Output Clock Skew
Period Jitter
Half-Period Jitter
Input Clock Slew Rate
Output Clock Slew Rate
SYMBOL
f_CK
t_DC
t_STAB
t_JITCC
t_âˆ
t_SKO
t_JITPER
t_JITHPER
t_LSI
t_LSO
MIN
60
40
-
-75
-50
-
-75
-100
1.0
1.0
0°C ≤ T_A ≤ +70°C
VDD = +2.6V ±0.1V
NOMINAL
-
-
-
-
0
-
-
-
-
-
MAX
220
60
100
75
50
100
75
100
4
2
UNITS
MHz
%
ms
ps
ps
ps
ps
ps
V/ns
V/ns
NOTES
2, 3
4
5
6
6
7
NOTE:
1. The timing and switching specifications for the PLL listed above are critical for proper operation of DDR SDRAM Regis-
tered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed
information for this PLL is available in JEDEC Standard JESD82.
2. The PLL must be able to handle spread spectrum induced skew.
3. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to
meet the other timing parameters. (Used for low speed system debug.)
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its ref-
erence signal after power up.
5. Static Phase Offset does not include Jitter.
6. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each
other.
7. The Output Slew Rate is determined from the IBIS model:
V_DD
CDCV857
V_CK
R=60Ω
R=60Ω V_DD/2
V_CK
GND
pdf: 09005aef80f6b913, source: 09005aef80f6b41c
DDAF18C64_128x72G.fm - Rev. C 9/04 EN
22
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©2004 Micron Technology, Inc. All rights reserved.