MT4LSDT464AG Datasheet, PDF (21/28 Pages) Micron Technology – SDRAM Unbuffered DIMM (UDIMM)

32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Notes
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including ^tWR and PRECHARGE commands). CKE may be used
to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (^tRP) begins 7ns for -13E;
7.5ns for -133; and 7ns for -10E after the first clock delay, after the last WRITE is exe-
cuted. May not exceed limit set for precharge mode.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27. ^tAC for -133/-13E at CL = 3 with no load is 4.6ns and is guaranteed by design.
28. Parameter guaranteed by design.
29. For -13E, CL = 2 and ^tCK = 7.5ns; for -133, CL = 3 and ^tCK = 7.5ns; for -10E, CL = 2 and
t_{CK = 10ns.}
30. CKE is HIGH during refresh command period ^tRFC (MIN), else CKE is LOW. The IDD6
limit is actually a nominal value and does not result in a fail value.
31. Refer to device data sheet for timing waveforms.
32. The value of ^tRAS used in -13E speed grade modules is calculated from ^tRC - ^tRP.
33. Leakage number reflects the worst-case leakage possible through the module pin, not
what each memory device contributes.
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
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