MT4C1M16E5 Datasheet, PDF (21/24 Pages) Micron Technology – EDO DRAM

RAS#
V _IH
V _IL
CASL#/CASH#
V _IH
V _IL
ADDR ^VVIIHL
DQx
V
V
IOH
IOL
OE#
V _IH
V _IL
HIDDEN REFRESH CYCLE
(WE# = HIGH; OE# = LOW)
tRC
tRAS
tRP
tCRP
tRCD
tRSH
tASR
tAR
tRAD
tRAH
ROW
OPEN
tASC
tCAH
COLUMN
tAA
tRAC
tCAC
tCLZ
tOE
tORD
16Mb: 1 MEG x16
EDO DRAM
tRAS
tCHR
VALID DATA
tOFF
OPEN
tOD
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL
t_AA
t_AR
t_ASC
t_ASR
t_CAC
t_CAH
t_CHR
t_CLZ
t_CRP
t_OD
-5
MIN
MAX
25
38
0
0
13
8
8
0
5
0
12
-6
MIN
MAX
30
45
0
0
15
10
10
0
5
0
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
t_OE
t_OFF
t_ORD
t_RAC
t_RAD
t_RAH
t_RAS
t_RCD
t_RP
t_RSH
-5
MIN
MAX
12
0
12
0
50
9
9
50
10,000
11
30
13
-6
MIN
MAX
15
0
15
0
60
12
10
60
10,000
14
40
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 Meg x 16 EDO DRAM
D52_B.p65 – Rev. B; Pub. 3/01
21
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