MT4C1M16E5 Datasheet, PDF (1/24 Pages) Micron Technology – EDO DRAM

EDO DRAM
16Mb: 1 MEG x16
EDO DRAM
MT4C1M16E5 – 1 Meg x 16, 5V
MT4LC1M16E5 – 1 Meg x 16, 3.3V
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/products/datasheets/sdramds.html
FEATURES
• JEDEC- and industry-standard x16 timing,
functions, pinouts, and packages
• High-performance CMOS silicon-gate process
• Single power supply (+3.3V ±0.3V or 5V ±10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR), HIDDEN; optional self refresh (S)
• BYTE WRITE access cycles
• 1,024-cycle refresh (10 row, 10 column addresses)
• Extended Data-Out (EDO) PAGE MODE access
• 5V-tolerant inputs and I/Os on 3.3V devices
OPTIONS
• Voltages¹
3.3V
5V
• Refresh Addressing
1,024 (1K) rows
• Packages
Plastic SOJ (400 mil)
Plastic TSOP (400 mil)
• Timing
50ns access
60ns access
• Refresh Rates
Standard Refresh (16ms period)
Self Refresh (128ms period)
• Operating Temperature Range
Commercial (0^oC to +70^oC)
Extended (-20^oC to +80^oC)
MARKING
LC
C
E5
DJ
TG
-5
-6
None
S²
None
ET
Part Number Example:
MT4LC1M16E5TG-6
NOTE: 1. The third field distinguishes the low voltage offering: LC desig-
nates Vcc = 3.3V and C designates Vcc = 5V.
2. Available only on MT4LC1M16E5 (3.3V)
KEY TIMING PARAMETERS
SPEED
-5
-6
t_RC
84ns
104ns
t_RAC
50ns
60ns
t_PC
20ns
25ns
t_AA
25ns
30ns
t_CAC
15ns
17ns
t_CAS
8ns
10ns
PIN ASSIGNMENT (Top View)
44/50-Pin TSOP
42-Pin SOJ
VCC
1
DQ0
2
DQ1
3
DQ2
4
DQ3
5
VCC
6
DQ4
7
DQ5
8
DQ6
9
DQ7
10
NC
11
NC
15
NC
16
WE#
17
RAS#
18
NC
19
NC
20
A0
21
A1
22
A2
23
A3
24
VCC
25
50
VSS
49
DQ15
48
DQ14
47
DQ13
46
DQ12
45
VSS
44
DQ11
43
DQ10
42
DQ9
41
DQ8
40
NC
VCC
1
DQ0 2
DQ1 3
DQ2 4
DQ3 5
VCC
6
DQ4 7
DQ5 8
DQ6 9
DQ7 10
NC 11
NC 12
36
NC
35
CASL#
WE# 13
34
CASH#
RAS# 14
33
OE#
NC 15
32
A9
31
A8
30
A7
29
A6
NC 16
A0 17
A1 18
28
A5
A2 19
27
A4
26
VSS
A3 20
VCC 21
42 VSS
41 DQ15
40 DQ14
39 DQ13
38 DQ12
37 VSS
36 DQ11
35 DQ10
34 DQ9
33 DQ8
32 NC
31 CASL#
30 CASH#
29 OE#
28 A9
27 A8
26 A7
25 A6
24 A5
23 A4
22 VSS
NOTE: The "#" symbol indicates signal is active LOW.
1 MEG x 16 EDO DRAM PART NUMBERS
PART NUMBER
MT4LC1M16E5DJ-x
MT4LC1M16E5DJ-x S
MT4LC1M16E5TG-x
MT4LC1M16E5TG-x S
MT4C1M16E5DJ-x
MT4C1M16E5TG-x
Vcc REFRESH PACKAGE REFRESH
3.3V 1K 400-SOJ Standard
3.3V 1K
400-SOJ Self
3.3V 1K 400-TSOP Standard
3.3V 1K 400-TSOP Self
5V
1K
400-SOJ Standard
5V
1K 400-TSOP Standard
NOTE: “-x” indicates speed grade marking under timing
options.
GENERAL DESCRIPTION
The 1 Meg x 16 is a randomly accessed, solid-state
memory containing 16,777,216 bits organized in a x16
configuration. The 1 Meg x 16 has both BYTE WRITE
and WORD WRITE access cycles via two CAS# pins
(CASL# and CASH#). These function like a single CAS#
found on other DRAMs in that either CASL# or CASH#
will generate an internal CAS#.
The CAS# function and timing are determined by
the first CAS# (CASL# or CASH#) to transition LOW and
the last CAS# to transition back HIGH. Using only one
1 Meg x 16 EDO DRAM
D52_B.p65 – Rev. B; Pub. 3/01
1
©2001, Micron Technology, Inc
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.