MT48LC1M16A1 Datasheet, PDF (20/51 Pages) Micron Technology – SYNCHRONOUS DRAM

Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-
length WRITE burst may be immediately followed by a
subsequent READ command. Once the READ com-
mand is registered, the data inputs will be ignored, and
WRITEs will not be executed. An example is shown in
Figure 17. Data n + 1 is either the last of a burst of two,
or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be fol-
lowed by, or truncated with, a PRECHARGE command
to the same bank (provided that AUTO PRECHARGE
was not activated), and a full-page WRITE burst may
be truncated with a PRECHARGE command to the
same bank. The PRECHARGE command should be
issued ^tWR after the clock edge at which the last desired
T0
T1
T2
T3
CLK
16Mb: x16
IT SDRAM
input data element is registered. In addition, when
truncating a WRITE burst, the DQM signal must be
used to mask input data for the clock edge prior to, and
the clock edge coincident with, the PRECHARGE com-
mand. An example is shown in Figure 18. Data n + 1 is
either the last of a burst of two or the last desired of a
longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be
issued until ^tRP is met.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-
length burst with AUTO PRECHARGE. The disadvan-
tage of the PRECHARGE command is that it requires
that the command and address buses be available at the
appropriate time to issue the command; the advantage
of the PRECHARGE command is that it can be used to
truncate fixed-length or full-page bursts.
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DQ
DIN
n
DIN
DIN
a
x
DIN
m
NOTE: Each WRITE command may be to any bank.
DQM is LOW.
Figure 16
Random WRITE Cycles
T0
T1
T2
T3
T4
T5
CLK
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL b
DQ
DIN
n
DIN
n+1
DOUT
b
DOUT
b+1
NOTE: The WRITE command may be to any bank, and the READ command may
be to any bank. DQM is LOW. CAS latency = 2 for illustration.
Figure 17
WRITE to READ
T0
T1
CLK
t_{WR = 1 CLK (}t_CK t_WR)
DQM
COMMAND
WRITE
NOP
T2
T3
T4
PRECHARGE
t _RP
NOP
NOP
T5
ACTIVE
ADDRESS
BANK a,
COL n
DQ
DIN
n
BANK
(a or all)
t _WR
DIN
n+1
BANK a,
ROW
t_{WR = 2 CLK (}t_{CK <} t_WR)
DQM
COMMAND
WRITE
NOP
t _RP
NOP
PRECHARGE
NOP
ACTIVE
ADDRESS
BANK a,
COL n
DQ
DIN
n
DIN
n+1
BANK
(a or all)
t _WR
BANK a,
ROW
NOTE:
DQM could remain LOW in this example if the WRITE burst is a
fixed length of two. Future SDRAMs will require a ^tWR of at least
two clocks.
DON’T CARE
Figure 18
WRITE to PRECHARGE
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
20
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©1999, Micron Technology, Inc.