MT48LC1M16A1 Datasheet, PDF (19/51 Pages) Micron Technology – SYNCHRONOUS DRAM

16Mb: x16
IT SDRAM
WRITEs
WRITE bursts are initiated with a WRITE com-
mand, as shown in Figure 13.
The starting column and bank addresses are pro-
vided with the WRITE command and AUTO
PRECHARGE is either enabled or disabled for that
access. If AUTO PRECHARGE is enabled, the row being
accessed is precharged at the completion of the burst.
For the generic WRITE commands used in the follow-
ing illustrations, AUTO PRECHARGE is disabled.
During WRITE bursts, the first valid data-in element
will be registered coincident with the WRITE com-
mand. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQs will remain High-Z, and
any additional input data will be ignored (see Figure
14). A full-page burst will continue until terminated.
(At the end of the page it will wrap to column 0 and
continue.)
Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixed-
length WRITE burst may be immediately followed by
data for a subsequent WRITE command. The new
WRITE command can be issued on any clock following
the previous WRITE command, and the data provided
CLK
CKE HIGH
CS#
RAS#
coincident with the new command applies to the new
command. An example is shown in Figure 15. Data n
+ 1 is either the last of a burst of two, or the last desired
of a longer burst. The 1 Meg x 16 SDRAM uses a
pipelined architecture and therefore does not require
the 2n rule associated with a prefetch architecture. A
WRITE command can be initiated on any clock cycle
following a previous WRITE command. Full-speed,
random write accesses within a page can be performed
as shown in Figure 16.
T0
T1
T2
T3
CLK
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DQ
DIN
n
DIN
n+1
NOTE:
Burst length = 2. DQM is LOW.
Figure 14
WRITE Burst
T0
T1
T2
CLK
CAS#
WE#
A0-A7
A8-A9
COLUMN
ADDRESS
A10
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK 1
BA
BANK 0
Figure 13
WRITE Command
COMMAND
WRITE
NOP
ADDRESS
DQ
BANK,
COL n
DIN
n
DIN
n+1
WRITE
BANK,
COL b
DIN
b
NOTE: DQM is LOW. Each WRITE
command may be to any bank.
DON’T CARE
Figure 15
WRITE to WRITE
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
19
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©1999, Micron Technology, Inc.