MT18VDVF12872DG Datasheet, PDF (18/38 Pages) Micron Technology – DDR SDRAM VLP Registered DIMM

512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Electrical Specifications
Electrical Specifications
Table 11:
IDD Specifications and Conditions – 512MB
DDR SDRAM Components Only
Notes: 1–5, 8, 10, 12, 47; notes appear on pages 22–26; 0°C ≤ T_A ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V
Max
Parameter/Condition
Sym
-335
-262
-26A/
-265 Units Notes
OPERATING CURRENT: One device bank; Active-Precharge; ^tRC =
t_{RC (MIN);} t_{CK =} t_{CK (MIN); DQ, DM and DQS inputs changing once}
per clock cyle; Address and control inputs changing once every two
clock cycles
OPERATING CURRENT: One device bank; Active -Read Precharge;
Burst = 4; ^tRC = ^tRC (MIN); ^tCK = ^tCK (MIN); IOUT = 0mA; Address
and control inputs changing once per clock cycle
IDD0^a
IDD1^a
1,161
1,566
1,161
1,476
981
1,341
mA 20, 41
mA 20, 41
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks IDD2P^b
72
72
72
mA 21, 28,
idle; Power-down mode; ^tCK = ^tCK (MIN); CKE = (LOW)
43
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; ^tCK = IDD2F^b 900
810
810 mA 44
t_{CK MIN; CKE = HIGH; Address and other control inputs changing}
once per clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode; ^tCK = ^tCK (MIN); CKE = LOW
IDD3P^b
540
450
450 mA 21, 28,
43
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge; ^tRC = ^tRAS (MAX); ^tCK = ^tCK (MIN); DQ,
DM andDQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
bank active; Address and control inputs changing once per clock
cycle; ^tCK = ^tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle; ^tCK = ^tCK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle
AUTO REFRESH CURRENT
t_{REFC =} t_{RFC (MIN)}
t_{REFC = 7.8125µs}
IDD3N^b
IDD4R^a
IDD4W^a
IDD5^b
IDD5A^b
1,080
1,611
1,611
4,590
108
900
1,386
1,386
4,230
108
900
1,386
1,386
4,230
108
mA
mA 20, 41
mA 20
mA 20, 43
mA 24, 43
SELF REFRESH CURRENT: CKE ≤ 0.2V
OPERATING CURRENT: Four device bank interleaving READs (BL =
4) with auto precharge, ^tRC = ^tRC (MIN); ^tCK = ^tCK (MIN); Address
and control inputs change only during Active READ, or WRITE
commands
IDD6^b
IDD7^a
72
3,726
72
3,186
72
3,186
mA
9
mA 20, 42
Note:
a: Value calculated as one module rank in this operating condition, and all other module
ranks in IDD2p (CKE LOW) mode.
b: Value calculated reflects all module ranks in this operating condition.
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
18
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