MT4LC4M4B1 Datasheet, PDF (17/20 Pages) Micron Technology – DRAM

RAS# ^VVIIHL
CASL#/CASH# ^VVIIHL
ADDR
V _IH
V _IL
DQx
V _IOH
V _IOL
OE#
V
V
IH
IL
HIDDEN REFRESH CYCLE ¹
(WE# = HIGH; OE# = LOW)
tRAS
tRP
tRAS
tCRP
tRCD
tRSH
tCHR
tASR
tAR
tRAD
tRAH
ROW
OPEN
tASC
tCAH
COLUMN
tAA
tRAC
tCAC
tCLZ
t _OE
tORD
VALID DATA
4 MEG x 4
FPM DRAM
tOFF
OPEN
tOD
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL
t_AA
t_AR
t_ASC
t_ASR
t_CAC
t_CAH
t_CHR
t_CLZ
t_CRP
t_OD
-5
MIN
MAX
25
38
0
0
13
8
8
0
5
0
12
-6
MIN
MAX
30
45
0
0
15
10
10
0
5
0
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
t_OE
t_OFF
t_ORD
t_RAC
t_RAD
t_RAH
t_RAS
t_RCD
t_RP
t_RSH
-5
MIN
MAX
12
0
12
0
50
9
9
50
10,000
11
30
13
MIN
0
0
12
10
60
14
40
15
-6
MAX
15
15
60
10,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.
4 Meg x 4 FPM DRAM
D49_5V.p65 – Rev. 5/00
17
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