MT36VDDT51272G Datasheet, PDF (15/18 Pages) Micron Technology – DDR SDRAM RDIMM

1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM
Register and PLL Specifications
Table 14: PLL Specifications
CVF857 device or equivalent JESD82-1A
Parameter
DC high-level input voltage
DC low-level input voltage
Input voltage (limits)
Input differential-pair cross voltage
Input differential voltage
Input differential voltage
Input current
Dynamic supply current
Dynamic supply current
Dynamic supply current
Input capacitance
Symbol
VIH
VIL
VIN
VIX
VID(DC)
VID(AC)
II
IDDPD
IDDQ
IADD
CIN
Min
1.7
–0.3
–0.3
(VDDQ/2) - 0.2
0.36
0.70
–10
–
–
–
2.0
Max
VDDQ + 0.3
0.7
VDDQ + 0.3
(VDDQ/2) + 0.2
VDDQ + 0.6
VDDQ + 0.6
+10
200
300
12
3.5
Units
V
V
V
V
V
V
µA
µA
µA
mA
pF
Table 15: PLL Clock Driver Timing Requirements and Switching Characteristics
Parameter
Stabilization time
Input clock slew rate
SSC modulation frequency
SSC clock input frequency deviation
PLL loop bandwidth (–3dB from unity gain)
Symbol
t_L
t_slr(i)
–
–
–
Min
–
1.0
30
0
2.0
Max
100
4.0
50
–0.50
–
Units
µs
V/ns
kHz
%
MHz
Notes: 1. PLL timing and switching specifications are critical for proper operation of the DDR DIMM.
This is a subset of parameters for the specific PLL used. Detailed PLL information is available
in JEDEC Standard JESD82-1A.
PDF: 09005aef809d5451/Source: 09005aef807da325
dd36c128_256_512x72.fm - Rev. F 6/08 EN
15
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