MT28F008B5 Datasheet, PDF (13/30 Pages) Micron Technology – FLASH MEMORY

8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
ERASE Sequence
Executing an ERASE sequence sets all bits within a
block to logic 1. The command sequence necessary to
execute an ERASE is similar to that of a WRITE. To pro-
vide added security against accidental block erasure,
two consecutive command cycles are required to ini-
tiate an erase of a block. In the first cycle, addresses are
“Don’t Care,” and ERASE SETUP (20h) is given. In the
second cycle, VPP must be brought to VPPH, an address
within the block to be erased must be issued, and
ERASE CONFIRM (D0h) must be given. If a command
other than ERASE CONFIRM is given, the write and
erase status bits (SR4 and SR5) are set, and the device
is in the status register read mode.
After the ERASE CONFIRM (D0h) is issued, the ISM
starts the ERASE of the addressed block. Any READ
operation outputs the status register contents on
DQ0–DQ7. VPP must be held at VPPH until the ERASE is
completed (SR7 = 1). When the ERASE is completed,
the device is in the status register read mode until
another command is issued. Erasing the boot block
also requires that either the RP# pin be set to VHH or
the WP# pin be held HIGH at the same time VPP is set
to VPPH.
ERASE Suspension
The only command that may be issued while an
ERASE is in progress is ERASE SUSPEND. This com-
mand allows other commands to be executed while
pausing the ERASE in progress. When the device has
reached the erase suspend mode, the erase suspend
status bit (SR6) and ISM status bit (SR7) is set. The
device may now be given a READ ARRAY, ERASE
RESUME or READ STATUS REGISTER command. After
READ ARRAY has been issued, any location not within
the block being erased may be read. If ERASE RESUME
is issued before SR6 has been set, the device immedi-
ately proceeds with the ERASE in progress.
ERROR HANDLING
After the ISM status bit (SR7) has been set, the VPP
(SR3), write (SR4) and erase (SR5) status bits may be
checked. If one or a combination of these three bits
has been set, an error has occurred. The ISM cannot
reset these three bits. To clear these bits, CLEAR STA-
TUS REGISTER (50h) must be given. If the VPP status
bit (SR3) is set, further write or erase operations can-
not resume until the status register is cleared. Table 4
lists the combination of errors.
Table 4: Status Register Error Decode¹
STATUS BITS
SR5
SR4
SR3
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
ERROR DESCRIPTION
No errors
VPP voltage error
WRITE error
WRITE error, VPP voltage not valid at time of WRITE
ERASE error
ERASE error, VPP voltage not valid at time of ERASE CONFIRM
Command sequencing error or WRITE/ERASE error
Command sequencing error, VPP voltage error, with WRITE and ERASE errors
Notes: 1. SR3–SR5 must be cleared using CLEAR STATUS REGISTER.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
13Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.