MT4LC4M16F5 Datasheet, PDF (12/19 Pages) Micron Technology – DRAM

4 MEG x 16
FPM DRAM
RAS#
V _IH
V _IL
CAS# ^VVIIHL
ADDR ^VVIIHL
WE# ^VVIIHL
DQ
V
V
IOH
IOL
OE#
V _IH
V _IL
READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC
tRAS
tCRP
tRCD
tCSH
tRSH
tCAS
tASR
tAR
tRAD
tRAH
ROW
tASC
tCAH
COLUMN
tRCS
tRWD
tCWD
tAWD
tCWL
tRWL
tWP
tCLZ
OPEN
tAA
tRAC
tCAC
tOE
tDS
tDH
VALID D _OUT
tOD
VALID D _IN
tOEH
tRP
ROW
OPEN
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL
t_AA
t_AR
t_ASC
t_ASR
t_AWD
t_CAC
t_CAH
t_CAS
t_CLCH
t_CLZ
t_CRP
t_CSH
t_CWD
t_CWL
t_DH
t_DS
-5
MIN
MAX
25
40
0
0
48
13
8
13
10,000
5
3
5
50
36
13
8
0
-6
MIN
MAX
30
45
0
0
55
15
10
15
10,000
5
3
5
60
40
15
10
0
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
t_OD
t_OE
t_OEH
t_RAC
t_RAD
t_RAH
t_RAS
t_RCD
t_RCS
t_RP
t_RSH
t_RWC
t_RWD
t_RWL
t_WP
-5
MIN
MAX
3
13
13
13
50
13
8
50
10,000
18
0
30
13
131
73
13
8
-6
MIN
MAX
3
15
15
15
60
15
10
60
10,000
20
0
40
15
155
85
15
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4 Meg x 16 FPM DRAM
D28_2.p65 – Rev. 5/00
12
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