MT4LC4M16F5 Datasheet, PDF (1/19 Pages) Micron Technology – DRAM

DRAM
MT4LC4M16F5
4 MEG x 16
FPM DRAM
For the latest data sheet, please refer to the Micron
Web site: www.micron.com/mti/msp/html/
datasheet.html
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x16 pinout, timing, functions,
and packages
• 12 row, 10 column addresses
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compatible
• FAST PAGE MODE (FPM) access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
OPTIONS
• Plastic Package
50-pin TSOP (400 mil)
MARKING
TG
• Timing
50ns access
-5
60ns access
-6
• Refresh Rate
Standard Refresh
None
Part Number Example
MT4LC4M16F5TG-5
KEY TIMING PARAMETERS
SPEED
-5
-6
t_RC
90ns
110ns
t_RAC
50ns
60ns
t_PC
30ns
35ns
t_AA
25ns
30ns
t_CAC
13ns
15ns
GENERAL DESCRIPTION
The 4 Meg x 16 DRAM is a high-speed CMOS,
dynamic random-access memory device containing
67,108,864 bits organized in a x16 configuration. The
MT4LC4M16F5 is functionally organized as 4,194,304
locations containing 16 bits each. The 4,194,304
memory locations are arranged in 4,096 rows by 1,024
columns. During READ or WRITE cycles, each location
is uniquely addressed via the address bits: 12 row-
address bits (A0-A11) and 10 column-address bits (A0-
A9). In addition, both byte and word accesses are
supported via the two CAS# pins (CASL# and CASH#).
The CAS# functionality and timing related to address
and control functions (e.g., latching column addresses
or selecting CBR REFRESH) are such that the internal
PIN ASSIGNMENT (Top View)
50-Pin TSOP
VCC
1
DQ0
2
DQ1
3
DQ2
4
DQ3
5
VCC
6
DQ4
7
DQ5
8
DQ6
9
DQ7
10
NC
11
VCC
12
WE#
13
RAS#
14
NC
15
NC
16
NC
17
NC
18
A0
19
A1
20
A2
21
A3
22
A4
23
A5
24
VCC
25
50
VSS
49
DQ15
48
DQ14
47
DQ13
46
DQ12
45
VSS
44
DQ11
43
DQ10
42
DQ9
41
DQ8
40
NC
39
VSS
38
CASL#
37
CASH#
36
OE#
35
NC
34
NC
33
NC
32
A11
31
A10
30
A9
29
A8
28
A7
27
A6
26
VSS
NOTE: 1. The # symbol indicates signal is active LOW.
CAS# signal is determined by the first external CAS#
signal (CASL# or CASH#) to transition LOW and the last
to transition back HIGH. The CAS# functionality and
timing related to driving or latching data are such that
each CAS# signal independently controls the associ-
ated eight DQ pins.
The row address is latched by the RAS# signal, then
the column address by CAS#. The device provides FAST-
PAGE-MODE operation, allowing for fast successive
data operations (READ, WRITE, or READ-MODIFY-
WRITE) within a given row.
The MT4LC4M16F5 must be refreshed periodi-
cally in order to retain stored data.
4 Meg x 16 FPM DRAM
D28_2.p65 – Rev. 5/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.