MT16HTF6464AY Datasheet, PDF (11/21 Pages) Micron Technology – DDR2 SDRAM Unbuffered DIMM

512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Electrical Specifications
Table 9:
DDR2 IDD Specifications and Conditions – 2GB
Values shown for DDR2 SDRAM components only
Parameter/Condition
Symbol
Operating one device bank active-precharge current; ^tCK = ^tCK (IDD),
t_{RC =} t_{RC (IDD),} t_{RAS =} t_{RAS MIN (IDD); CKE is HIGH, S# is HIGH between}
valid commands; Address bus inputs are switching; Data bus inputs are
switching
IDD0^a
Operating one device bank active-read-precharge current; IOUT =
0mA; BL = 4, CL = CL (IDD), AL = 0; ^tCK = ^tCK (IDD), ^tRC = ^tRC (IDD), ^tRAS =
t_{RAS MIN (IDD),} t_{RCD =} t_{RCD (IDD); CKE is HIGH, S# is HIGH between valid}
commands; Address bus inputs are switching; Data pattern is same as
IDD4W
Precharge power-down current; All device banks idle; ^tCK = ^tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge quiet standby current; All device banks idle; ^tCK = ^tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current; All device banks idle; ^tCK = ^tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current; All device banks open; ^tCK Fast PDN exit
= ^tCK (IDD); CKE is LOW; Other control and address bus MR[12] = 0
inputs are stable; Data bus inputs are floating
Slow PDN exit
MR[12] = 1
Active standby current; All device banks open; ^tCK = ^tCK (IDD), ^tRAS =
t_{RAS MAX (IDD),} t_{RP =} t_{RP (IDD); CKE is HIGH, S# is HIGH between valid}
commands; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD1^a
IDD2P^b
IDD2Q^b
IDD2N^b
IDD3P^b
IDD3N^b
Operating burst write current; All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; ^tCK = ^tCK (IDD), ^tRAS = ^tRAS MAX (IDD),
t_{RP =} t_{RP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address}
bus inputs are switching; Data bus inputs are switching
IDD4W^a
Operating burst read current; All device banks open; Ccontinuous burst
reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; ^tCK = ^tCK (IDD), ^tRAS = ^tRAS
MAX (IDD), ^tRP = ^tRP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are
switching
Burst refresh current; ^tCK = ^tCK (IDD); REFRESH command at every ^tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other
control and address bus inputs are switching; Data bus inputs are
switching
IDD4R^a
IDD5^b
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
IDD6^b
Operating device bank interleave read current; All device banks
interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = ^tRCD (IDD) - 1 ×
t_{CK (IDD);} t_{CK =} t_{CK (IDD),} t_{RC =} t_{RC (IDD),} t_{RRD =} t_{RRD (IDD),} t_{RCD =} t_RCD
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are stable during DESELECTs; Data bus inputs are switching; See
IDD7 conditions in component data sheet for detail
IDD7^a
-80E
856
936
112
1,040
1,120
720
160
1,200
1,536
1,576
4,480
112
2,736
-667
776
856
112
880
960
640
160
1,120
1,336
1,336
4,160
112
2,456
-53E
696
816
112
656
720
480
160
880
1,096
1,216
4,000
112
2,376
-40E
616
696
112
560
640
400
160
720
936
936
3,520
112
2,136
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes:
1. a = Value calculated as one module rank in this operating condition, and all other module
ranks in IDD2P (CKE LOW).
2. b = Value calculated reflects all module ranks in this operating condition.
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
11
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