MT58L1MY18D Datasheet, PDF (1/34 Pages) Micron Technology – 16Mb SYNCBURST™ SRAM

ADVANCE
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
16Mb SYNCBURST^™
SRAM
MT58L1MY18D, MT58V1MV18D,
MT58L512Y32D, MT58V512V32D,
MT58L512Y36D, MT58V512V36D
3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD, 2.5V
I/O, Pipelined, Double-Cycle Deselect
FEATURES
• Fast clock and OE# access times
• Single +3.3V ±0.165Vor 2.5V ±0.125V power supply
(VDD)
• Separate +3.3V or 2.5V isolated output buffer
supply (VDDQ)
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL
WRITE
• Three chip enables for simple depth expansion and
address pipelining
• Clock-controlled and registered addresses, data I/Os
and control signals
• Internally self-timed WRITE cycle
• Burst control (interleaved or linear burst)
• Automatic power-down
• 100-pin TQFP package
• 165-pin FBGA package
• Low capacitive bus loading
• x18, x32, and x36 versions available
OPTIONS
TQFP MARKING*
• Timing (Access/Cycle/MHz)
3.5ns/6ns/166 MHz
-6
4.0ns/7.5ns/133 MHz
-7.5
5ns/10ns/100 MHz
-10
• Configurations
3.3V VDD, 3.3V or 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
2.5V VDD, 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
MT58L1MY18D
MT58L512Y32D
MT58L512Y36D
MT58V1MV18D
MT58V512V32D
MT58V512V36D
• Packages
100-pin TQFP (3-chip enable)
T
165-pin FBGA
F
• Operating Temperature Range
Commercial (0ºC to +70ºC)
None
*See page 34 for FBGA package marking guide.
Part Number Example:
MT58L1MY18DT-7.5
100-Pin TQFP¹
165-Pin FBGA
(Preliminary Package Data)
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
GENERAL DESCRIPTION
The Micron^® SyncBurst^™ SRAM family employs high-
speed, low-power CMOS designs that are fabricated
using an advanced CMOS process.
Micron’s 16Mb SyncBurst SRAMs integrate a 1 Meg x
18, 512K x 32, or 512K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single-clock in-
put (CLK). The synchronous inputs include all addresses,
all data inputs, active LOW chip enable (CE#), two
additional chip enables for easy depth expansion (CE2,
CE2#), burst control inputs (ADSC#, ADSP#, ADV#),
byte write enables (BWx#) and global write (GW#). Note
that CE2# is not available on the T Version.
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is also
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.