MT55L512L18P Datasheet, PDF (1/25 Pages) Micron Technology – 8Mb ZBT SRAM

8Mb
ZBT^® SRAM
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
MT55L512L18P, MT55L512V18P,
MT55L256L32P, MT55L256V32P,
MT55L256L36P, MT55L256V36P
3.3V VDD, 3.3V or 2.5V I/O
FEATURES
• High frequency and 100 percent bus utilization
• Fast cycle times: 6ns, 7.5ns and 10ns
• Single +3.3V ±5% power supply (VDD)
• Separate +3.3V or +2.5V isolated output buffer
supply (VDDQ)
• Advanced control logic for minimum control
signal interface
• Individual BYTE WRITE controls may be tied LOW
• Single R/W# (read/write) control pin
• CKE# pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• Clock-controlled and registered addresses, data
I/Os and control signals
• Internally self-timed, fully coherent WRITE
• Internally self-timed, registered outputs to
eliminate the need to control OE#
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Linear or Interleaved Burst Modes
• Burst feature (optional)
• Pin/function compatibility with 2Mb, 4Mb, and
18Mb ZBT SRAM
• Automatic power-down
• 100-pin TQFP package
• 165-pin FBGA package
OPTIONS
• Timing (Access/Cycle/MHz)
3.5ns/6ns/166 MHz
4.2ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
3.3V I/O
512K x 18
256K x 32
256K x 36
2.5V I/O
512K x 18
256K x 32
256K x 36
• Package
100-pin TQFP
165-pin, 13mm x 15mm FBGA
• Operating Temperature Range
Commercial (0ºC to +70ºC)
Industrial (-40°C to +85°C)**
MARKING
-6
-7.5
-10
MT55L512L18P
MT55L256L32P
MT55L256L36P
MT55L512V18P
MT55L256V32P
MT55L256V36P
T
F*
None
IT
Part Number Example:
MT55L256L32PT-7.5
100-Pin TQFP¹
165-Pin FBGA
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
GENERAL DESCRIPTION
The Micron^® Zero Bus Turnaround^™ (ZBT^®) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
Micron’s 8Mb ZBT SRAMs integrate a 512K x 18,
256K x 32, or 256K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. These SRAMs are optimized for 100 percent
bus utilization, eliminating any turnaround cycles for
READ to WRITE, or WRITE to READ, transitions. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).
The synchronous inputs include all addresses, all data
inputs, chip enable (CE#), two additional chip enables
for easy depth expansion (CE2, CE2#), cycle start input
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_C.p65 – Rev. 2/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.