MT4LC4M4E8 Datasheet, PDF (1/23 Pages) Micron Technology – 4 MEG x 4 EDO DRAM

TECHNOLOGY, INC.
DRAM
4 MEG x 4
EDO DRAM
MT4LC4M4E8, MT4C4M4E8
MT4LC4M4E9, MT4C4M4E9
FEATURES
• Industry-standard x4 pinout, timing, functions and
packages
• State-of-the-art, high-performance, low-power CMOS
silicon-gate process
• Single power supply (+3.3V ±0.3V or +5V ±10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, HIDDEN and CAS#-
BEFORE-RAS# (CBR)
• Optional Self Refresh (S) for low-power data retention
• 11 row, 11 column addresses (2K refresh) or
12 row, 10 column addresses (4K refresh)
• Extended Data-Out (EDO) PAGE MODE access cycle
• 5V-tolerant inputs and I/Os on 3.3V devices
OPTIONS
MARKING
• Voltages
3.3V
LC
5V
C
• Refresh Addressing
2,048 (i.e. 2K) Rows
E8
4,096 (i.e. 4K) Rows
E9
• Packages
Plastic SOJ (300 mil)
DJ
Plastic TSOP (300 mil)
TG
• Timing
50ns access
-5
60ns access
-6
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
None
S
• Part Number Example: MT4LC4M4E8DJ-6
Note: The 4 Meg x 4 EDO DRAM base number differentiates the offerings in
two places - MT4LC4M4E8. The third field distinguishes the low voltage
offering: LC designates VCC = 3.3V and C designates VCC = 5V. The fifth field
distinguishes various options: E8 designates a 2K refresh and E9 designates a
4K refresh for EDO DRAMs.
KEY TIMING PARAMETERS
SPEED
-5
-6
t_RC
84ns
104ns
t_RAC
50ns
60ns
t_PC
20ns
25ns
t_AA
25ns
30ns
t_CAC
13ns
15ns
t_CAS
8ns
10ns
PIN ASSIGNMENT (Top View)
24/26-Pin SOJ
(DA-2)
24/26-Pin TSOP
(DB-2)
VCC 1
DQ1 2
DQ2 3
WE# 4
RAS# 5
*NC/A11 6
A10 8
A0 9
A1 10
A2 11
A3 12
VCC 13
26 VSS
VCC 1
25 DQ4
DQ1 2
24 DQ3
DQ2 3
23
22
CAS#
WE#
OE#
RAS#
*NC/A11
4
5
6
21 A9
19 A8
18 A7
17 A6
16 A5
15 A4
14 VSS
A10 8
A0 9
A1 10
A2 11
A3 12
VCC 13
26 VSS
25 DQ4
24 DQ3
23 CAS#
22 OE#
21 A9
19 A8
18 A7
17 A6
16 A5
15 A4
14 VSS
* NC on 2K refresh and A11 on 4K refresh options.
Note: The “#” symbol indicates signal is active LOW.
4 MEG x 4 EDO DRAM PART NUMBERS
PART NUMBER
MT4LC4M4E8DJ
MT4LC4M4E8DJS
MT4LC4M4E8TG
MT4LC4M4E8TGS
MT4LC4M4E9DJ
MT4LC4M4E9DJS
MT4LC4M4E9TG
MT4LC4M4E9TGS
MT4C4M4E8DJ
MT4C4M4E8DJS
MT4C4M4E8TG
MT4C4M4E8TGS
MT4C4M4E9DJ
MT4C4M4E9DJS
MT4C4M4E9TG
MT4C4M4E9TGS
Vcc
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
5V
5V
5V
5V
5V
5V
5V
5V
REFRESH
2K
2K
2K
2K
4K
4K
4K
4K
2K
2K
2K
2K
4K
4K
4K
4K
PACKAGE
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
REFRESH
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
GENERAL DESCRIPTION
The 4 Meg x 4 DRAM is a randomly accessed, solid-state
memory containing 16,777,216 bits organized in a x4 con-
figuration. RAS# is used to latch the row address (first 11
bits for 2K and first 12 bits for 4K). Once the page has been
opened by RAS#, CAS# is used to latch the column address
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997, Micron Technology, Inc.