MT4LC16M4G3 Datasheet, PDF (1/22 Pages) Micron Technology – DRAM

DRAM
16 MEG x 4
EDO DRAM
MT4LC16M4G3, MT4LC16M4H9
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/mti/msp/html/datasheet.html
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x4 pinout, timing, functions,
and packages
• 12 row, 12 column addresses (H9) or
13 row, 11 column addresses (G3)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compat-
ible
• Extended Data-Out (EDO) PAGE MODE access
• Optional self refresh (S) for low-power data
retention
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
OPTIONS
• Refresh Addressing
4,096 (4K) rows
8,192 (8K) rows
MARKING
H9
G3
• Plastic Packages
32-pin SOJ (400 mil)
DJ
32-pin TSOP (400 mil)
TG
• Timing
50ns access
-5
60ns access
-6
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
None
S*
NOTE: 1. The 16 Meg x 4 EDO DRAM base number
differentiates the offerings in one place—
MT4LC16M4H9. The fifth field distinguishes the
address offerings: H9 designates 4K addresses and
G3 designates 8K addresses.
2. The “#” symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
MT4LC16M4H9DJ-6
KEY TIMING PARAMETERS
SPEED
-5
-6
t_RC
84ns
104ns
t_RAC
50ns
60ns
t_PC
20ns
25ns
t_AA
25ns
30ns
t_CAC
13ns
15ns
t_CAS
8ns
10ns
PIN ASSIGNMENT (Top View)
32-Pin SOJ
32-Pin TSOP
VCC 1
DQ0 2
DQ1 3
NC 4
NC 5
NC 6
NC 7
WE# 8
RAS# 9
A0 10
A1 11
A2 12
A3 13
A4 14
A5 15
VCC 16
32 Vss
31 DQ3
30 DQ2
29 NC
28 NC
27 NC
VCC 1
DQ0 2
DQ1 3
NC 4
NC 5
NC 6
NC 7
26 CAS#
WE# 8
25 OE#
RAS# 9
24 NC/A12** ^{A0 10}
23 A11
A1 11
22 A10
A2 12
A3 13
21 A9
A4 14
20 A8
A5 15
19 A7
VCC 16
18 A6
17 Vss
**NC on H9 version, A12 on G3 version
32 Vss
31 DQ3
30 DQ2
29 NC
28 NC
27 NC
26 CAS#
25 OE#
24 NC/A12**
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 Vss
16 MEG x 4 EDO DRAM PART NUMBERS
PART NUMBER
MT4LC16M4H9DJ-x
MT4LC16M4H9DJ-x S
MT4LC16M4H9TG-x
MT4LC16M4H9TG-x S
MT4LC16M4G3DJ-x
MT4LC16M4G3DJ-x S
MT4LC16M4G3TG-x
MT4LC16M4G3TG-x S
x = speed
REFRESH
ADDRESSING
4K
4K
4K
4K
8K
8K
8K
8K
PACKAGE
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
REFRESH
Standard
Self
Standard
Self
Standard
Self
Standard
Self
GENERAL DESCRIPTION
The 16 Meg x 4 DRAM is a high-speed CMOS,
dynamic random-access memory device containing
67,108,864 bits and designed to operate from 3V to
3.6V. The MT4LC16M4H9 and MT4LC16M4G3 are
functionally organized as 16,777,216 locations con-
taining 4 bits each. The 16,777,216 memory locations
are arranged in 4,096 rows by 4,096 columns on the H9
version and 8,192 rows by 2,048 columns on the G3
version. During READ or WRITE cycles, each location is
16 Meg x 4 EDO DRAM
D22_2.p65 – Rev. 5/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.