MT4C1M16C3 Datasheet, PDF (1/22 Pages) Micron Technology – FPM DRAM

FPM DRAM
1 MEG x 16
FPM DRAM
MT4C1M16C3, MT4LC1M16C3
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/datasheets
FEATURES
• JEDEC- and industry-standard x16 timing,
functions, pinouts, and packages
• High-performance, low-power CMOS silicon-gate
process
• Single power supply (+3.3V ±0.3V or 5V ±0.5V)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN
• Optional self refresh (S) for low-power data
retention
• BYTE WRITE and BYTE READ access cycles
• 1,024-cycle refresh (10 row, 10 column addresses)
• FAST-PAGE-MODE (FPM) access
OPTIONS
• Voltage¹
3.3V
5V
MARKING
LC
C
• Packages
Plastic SOJ (400 mil)
Plastic TSOP (400 mil)
• Timing
50ns access
60ns access
• Refresh Rates
Standard Refresh (16ms period)
Self Refresh (128ms period)
• Operating Temperature Range
Commercial (0^oC to +70^oC)
Extended (-20^oC to +80^oC)
DJ
TG
-5
-6
None
S²
None
ET³
Part Number Example:
MT4LC1M16C3DJ-5
NOTE: 1. The third field distinguishes the low voltage offering:
LC designates VCC = 3.3V and C designates VCC = 5V.
2. Contact factory for availability.
3. Available only on MT4C1M16C3 (5V)
KEY TIMING PARAMETERS
SPEED
-5
-6
t_RC
84ns
110ns
t_RAC
50ns
60ns
t_PC
20ns
35ns
t_AA
25ns
30ns
t_CAC
15ns
15ns
t_RP
30ns
40ns
PIN ASSIGNMENT (Top View)
42-Pin SOJ
44/50-Pin TSOP
VCC 1
DQ0 2
DQ1 3
DQ2 4
DQ3 5
VCC 6
DQ4 7
DQ5 8
DQ6 9
DQ7 10
NC 11
NC 12
WE# 13
RAS# 14
NC 15
NC 16
A0 17
A1 18
A2 19
A3 20
VCC 21
42 VSS
VCC
1
41 DQ15
DQ0
DQ1
2
3
40 DQ14
DQ2
4
39 DQ13
DQ3
5
38 DQ12
VCC
DQ4
6
7
37 VSS
DQ5
8
36 DQ11
DQ6
9
DQ7
10
35 DQ10
NC
11
34 DQ9
33 DQ8
32 NC
NC
15
31 CASL#
NC
16
30
CASH#
WE#
RAS#
17
18
29 OE#
NC
19
28 A9
27 A8
NC
20
A0
21
A1
22
26 A7
A2
23
25 A6
24 A5
A3
24
VCC
25
23 A4
22 VSS
50
VSS
49
DQ15
48
DQ14
47
DQ13
46
DQ12
45
VSS
44
DQ11
43
DQ10
42
DQ9
41
DQ8
40
NC
36
NC
35
CASL#
34
CASH#
33
OE#
32
A9
31
A8
30
A7
29
A6
28
A5
27
A4
26
VSS
NOTE: The # symbol indicates signal is active LOW.
1 MEG x 16 FPM DRAM PART NUMBERS
PART NUMBER
MT4LC1M16C3DJ-6
MT4LC1M16C3DJ-6 S
MT4LC1M16C3TG-6
MT4LC1M16C3TG-6 S
MT4C1M16C3DJ-6
MT4C1M16C3TG-6
SUPPLY PACKAGE REFRESH
3.3V
SOJ Standard
3.3V
SOJ
Self
3.3V
TSOP Standard
3.3V
TSOP
Self
5V
SOJ Standard
5V
TSOP Standard
GENERAL DESCRIPTION
The 1 Meg x 16 DRAM is a randomly accessed, solid-
state memory containing 16,777,216 bits organized in
a x16 configuration. The 1 Meg x 16 DRAM has both
BYTE WRITE and WORD WRITE access cycles via two
CAS# pins (CASL# and CASH#). These function identi-
cally to a single CAS# on other DRAMs in that either
CASL# or CASH# will generate an internal CAS#.
The CAS# function and timing are determined by
the first CAS# (CASL# or CASH#) to transition LOW and
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.