MT48LC32M4A2 Datasheet, PDF (1/59 Pages) Micron Technology – SYNCHRONOUS DRAM

128Mb: x4, x8, x16
SDRAM
SYNCHRONOUS
DRAM
MT48LC32M4A2 – 8 Meg x 4 x 4 banks
MT48LC16M8A2 – 4 Meg x 8 x 4 banks
MT48LC8M16A2 – 2 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/dramds
FEATURES
• PC100-, and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode; standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
OPTIONS
• Configurations
32 Meg x 4 (8 Meg x 4 x 4 banks)
16 Meg x 8 (4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
• WRITE Recovery (^tWR)
t_{WR = “2 CLK”}1
• Package/Pinout
Plastic Package – OCPL²
54-pin TSOP II (400 mil)
60-ball FBGA (8mm x 16mm)
60-ball FBGA (11mm x 13mm)
• Timing (Cycle Time)
10ns @ CL = 2 (PC100)
7.5ns @ CL = 3 (PC133)
7.5ns @ CL = 2 (PC133)
• Self Refresh
Standard
Low power
• Operating Temperature Range
Commercial (0^oC to +70^oC)
Industrial (-40^oC to +85^oC)
MARKING
32M4
16M8
8M16
A2
TG
FB ^3,6
FC ^3,6
-8E ^3,4,5
-75
-7E
None
L
None
IT ³
Part Number Example:
MT48LC16M8A2TG-7E
NOTE: 1. Refer to Micron Technical Note: TN-48-05.
2. Off-center parting line.
3. Consult Micron for availability.
4. Not recommended for new designs.
5. Shown for PC100 compatability.
6. See page 59 for FBGA Device Marking Table.
PIN ASSIGNMENT (Top View)
x4 x8 x16
-
- VDD
NC DQ0 DQ0
-
- VDDQ
NC NC DQ1
DQ0 DQ1 DQ2
- - VssQ
NC NC DQ3
NC DQ2 DQ4
-
- VDDQ
NC NC DQ5
DQ1 DQ3 DQ6
- - VssQ
NC NC DQ7
-
- VDD
NC NC DQML
- - WE#
- - CAS#
- - RAS#
- - CS#
- - BA0
- - BA1
- - A10
- - A0
- - A1
- - A2
- - A3
-
- VDD
54-Pin TSOP
1
54
2
53
3
52
4
51
5
50
6
49
7
48
8
47
9
46
10
45
11
44
12
43
13
42
14
41
15
40
16
39
17
38
18
37
19
36
20
35
21
34
22
33
23
32
24
31
25
30
26
29
27
28
x16 x8 x4
Vss - -
DQ15 DQ7 NC
VssQ - -
DQ14 NC NC
DQ13 DQ6 DQ3
VDDQ -
-
DQ12 NC NC
DQ11 DQ5 NC
VssQ - -
DQ10 NC NC
DQ9 DQ4 DQ2
VDDQ -
-
DQ8 NC NC
Vss - -
NC - -
DQMH DQM DQM
CLK - -
CKE - -
NC - -
A11 - -
A9 - -
A8 - -
A7 - -
A6 - -
A5 - -
A4 - -
Vss - -
Note: The # symbol indicates signal is active LOW. A dash (–)
indicates x8 and x4 pin function is same as x16 pin function.
32 Meg x 4
16 Meg x 8
8 Meg x 16
Configuration
8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
Refresh Count
4K
4K
4K
Row Addressing
4K (A0–A11)
4K (A0–A11)
4K (A0–A11)
Bank Addressing
4 (BA0, BA1)
4 (BA0, BA1)
4 (BA0, BA1)
Column Addressing 2K (A0–A9, A11)
1K (A0–A9)
512 (A0–A8)
KEY TIMING PARAMETERS
SPEED
CLOCK
ACCESS TIME SETUP
GRADE FREQUENCY CL = 2* CL = 3* TIME
-7E
143 MHz
–
5.4ns 1.5ns
-7E
-75
-8E ^3,4,5
133 MHz
133 MHz
125 MHz
5.4ns
–
–
–
5.4ns
6ns
1.5ns
1.5ns
2ns
-75
100 MHz
6ns
-8E ^{3 ,4,5}
100 MHz
6ns
–
1.5ns
–
2ns
HOLD
TIME
0.8ns
0.8ns
0.8ns
1ns
0.8ns
1ns
*CL = CAS (READ) latency
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.