PIC16HV540 Datasheet, PDF(9/36 Page) Microchip Technology – Enhanced PIC16C54 EPROM-Based 8-Bit CMOS Microcontroller With On-Chip Voltage Regulator

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

PIC16HV540 Datasheet, PDF (9/36 Pages) Microchip Technology – Enhanced PIC16C54 EPROM-Based 8-Bit CMOS Microcontroller With On-Chip Voltage Regulator

◁

PIC16HV540

TABLE 5-2: INSTRUCTION SET SUMMARY

Mnemonic,

Operands

Description

12-Bit Opcode

Status

Cycles MSb

LSb Affected Notes

ADDWF f,d Add W and f

ANDWF f,d AND W with f

CLRF

Clear f

CLRW

Clear W

COMF

f, d Complement f

DECF

f, d Decrement f

DECFSZ f, d Decrement f, Skip if 0

INCF

f, d Increment f

INCFSZ f, d Increment f, Skip if 0

IORWF

f, d Inclusive OR W with f

MOVF

f, d Move f

MOVWF f

Move W to f

NOP

No Operation

RLF

f, d Rotate left f through Carry

RRF

f, d Rotate right f through Carry

SUBWF f, d Subtract W from f

SWAPF f, d Swap f

XORWF f, d Exclusive OR W with f

1 0001 11df ffff

1 0001 01df ffff

1 0000 011f ffff

1 0000 0100 0000

1 0010 01df ffff

1 0000 11df ffff

1(2) 0010 11df ffff

1 0010 10df ffff

1(2) 0011 11df ffff

1 0001 00df ffff

1 0010 00df ffff

1 0000 001f ffff

1 0000 0000 0000

1 0011 01df ffff

1 0011 00df ffff

1 0000 10df ffff

1 0011 10df ffff

1 0001 10df ffff

C,DC,Z

None

C,DC,Z

None

1,2,4

2,4

1,4

2,4

1,2,4

2,4

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b Bit Clear f

f, b Bit Set f

f, b Bit Test f, Skip if Clear

f, b Bit Test f, Skip if Set

1 0100 bbbf ffff None 2,4

1 0101 bbbf ffff None 2,4

1 (2) 0110 bbbf ffff None

1 (2) 0111 bbbf ffff None

LITERAL AND CONTROL OPERATIONS

ANDLW k

CALL

CLRWDT k

GOTO

IORLW

MOVLW k

OPTION k

RETLW k

SLEEP

TRIS

XORLW k

AND literal with W

Call subroutine

Clear Watchdog Timer

Unconditional branch

Inclusive OR Literal with W

Move Literal to W

Load OPTION register

Return, place Literal in W

Go into standby mode

Load TRIS register

Exclusive OR Literal to W

1 1110 kkkk kkkk

2 1001 kkkk kkkk None

1 0000 0000 0100 TO, PD

2 101k kkkk kkkk None

1 1101 kkkk kkkk

1 1100 kkkk kkkk None

1 0000 0000 0010 None

2 1000 kkkk kkkk None

1 0000 0000 0011 TO, PD

1 0000 0000 0fff None

1 1111 kkkk kkkk

Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for GOTO.

(See individual device data sheets, Memory Section/Indirect Data Addressing, INDF and FSR Registers)

2: When an I/O register is modiï¬ed as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' for a pin conï¬gured as input and is driven

low by an external device, the data will be written back with a '0'.

3: The instruction TRIS f, where f = 5 or 6 causes the contents of the W register to be written to the tristate

latches of PORTA or B respectively. A '1' forces the pin to a hi-impedance state and disables the output buffers.

4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared

(if assigned to TMR0).

Preliminary

DS40197A-page 9

▷