MCP47A1T-A0E-LT Datasheet, PDF (9/70 Pages) Microchip Technology – 6-Bit Volatile DAC with Command Code

MCP47A1
TABLE 1-2: I²C BUS DATA REQUIREMENTS (SLAVE MODE)
I²C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40C  TA  +125C (Extended)
Operating Voltage VDD range is described in AC/DC characteristics
Parame-
ter No.
Sym
Characteristic
Min
Max Units
Conditions
100
T_HIGH Clock high time 100 kHz mode
4000
—
ns 1.8V-5.5V
400 kHz mode
600
—
ns 2.7V-5.5V
101
T_LOW Clock low time 100 kHz mode
4700
—
ns _1.8V-5.5V
102A^{(5) TRSCL SCL rise time}
102B^{(5) TRSDA SDA rise time}
103A ^{(5) TFSCL SCL fall time}
103B ^{(5) TFSDA SDA fall time}
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
1300
—
20 + 0.1Cb
—
20 + 0.1Cb
—
20 + 0.1Cb
—
20 + 0.1Cb⁽⁵⁾
—
1000
300
1000
300
300
40
300
300
ns 2.7V-5.5V
ns C_b is specified to be from
ns ^{10 to 400 pF}
ns C_b is specified to be from
ns ^{10 to 400 pF}
ns C_b is specified to be from
ns ^{10 to 400 pF}
ns C_b is specified to be from
ns ^{10 to 400 pF}
106 THD:DAT Data input hold 100 kHz mode
time
400 kHz mode
107 TSU:DAT Data input
setup time
100 kHz mode
400 kHz mode
109
T_AA Output valid
100 kHz mode
from clock
400 kHz mode
0
—
ns _{1.8V-5.5V (Note 6)}
0
—
ns 2.7V-5.5V (Note 6)
250
—
ns Note 5
100
—
ns
—
3450 ns Note 5
—
900 ns
110
T_BUF Bus free time 100 kHz mode
4700
400 kHz mode
1300
—
ns Time the bus must be free
—
ns ^{before a new transmission}
can start
Note 1:
2:
3:
4:
5:
6:
T_SP Input filter spike 100 kHz mode
—
suppression
400 kHz mode
—
(SDA and SCL)
50 ns Philips Spec states N.A.
50 ns
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A fast-mode (400 kHz) I²C-bus device can be used in a standard-mode (100 kHz) I²C-bus system, but the
requirement tsu; DAT  250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I²C bus specification) before
the SCL line is released.
The MCP47A1 device must provide a data hold time to bridge the undefined part between VIH and VIL of
the falling edge of the SCL signal. This specification is not a part of the I²C specification, but must be
tested in order to guarantee that the output data will meet the setup and hold specifications for the
receiving device.
Use C_b in pF for the calculations.
Not tested.
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
 2012 Microchip Technology Inc.
DS25154A-page 9