KSZ8081MLX Datasheet, PDF (9/56 Pages) Microchip Technology – 10BASE-T/100BASE-TX Physical Layer Transceiver

KSZ8081MLX
TABLE 2-1: SIGNALS - KSZ8081MLX (CONTINUED)
Pin
Number
44
45
46
47
48
Note 2-1
Note 2-2
Note 2-3
Pin
Name
Type
Note
2-1
Description
TEST/NC
Ipd
No Connect for normal operation, an external pull-up resistor for NAND tree
testing.
NC
— No Connect. This pin is not bonded and can be left floating.
NC
— No Connect. This pin is not bonded and can be left floating.
RST#
Ipu Chip Reset (active low).
NC
— No Connect. This pin is not bonded and can be left floating.
P = power supply
GND = ground
I = input
O = output
I/O = bi-directional
Ipu = Input with internal pull-up (see Electrical Characteristics for value).
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal
pull-up (see Electrical Characteristics for value).
MII RX Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0]
presents valid data to the MAC.
MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0]
presents valid data from the MAC.
2.1 Strap-In Options
The PHYAD[1:0] strap-in pin is latched at the de-assertion of reset. In some systems, the RMII MAC receive input pins
may drive high/low during power-up or reset, and consequently cause the PHYAD[1:0] strap-in pin, a shared pin with
the RMII CRS_DV signal, to be latched to the unintended high/low state. In this case an external pull-up (4.7 kΩ) or pull-
down (1.0 kΩ) should be added on the PHYAD[1:0] strap-in pin to ensure that the intended value is strapped-in correctly.
TABLE 2-2:
Pin Number
22
21
20
27
41
40
STRAP-IN OPTIONS - KSZ8081MLX
Pin Name
PHYAD2
PHYAD1
PHYAD0
CONFIG2
Type
Note 2-4
Ipd/O
Description
The PHY address is latched at de-assertion of reset and is configu-
rable to any value from 0 to 7. The default PHY address is 00001.
PHY address 00000 is enabled only if the B-CAST_OFF strap-in pin
is pulled high. PHY address Bits [4:3] are set to 00 by default.
The CONFIG[2:0] strap-in pins are latched at the de-assertion of
reset.
CONFIG1
CONFIG0
Ipd/O
CONFIG[2:0] Mode
000
MII (default)
110
MII back-to-back
001 – 101,
111
Reserved, not used
 2016 Microchip Technology Inc.
DS00002264A-page 9