93LCS56 Datasheet, PDF (9/12 Pages) Microchip Technology – 2K/4K 2.5V Microwire Serial EEPROM with Software Write Protect

93LCS56/66
FIGURE 2-10: PREN TIMING
PRE
PE
CS
TCSL
CLK
DI
1
0
0
1
1
DO = TRI-STATE
A EWEN cycle must precede a PREN cycle.
FIGURE 2-11: PRCLEAR TIMING
PRE
X
•••
X
6 DON'T CARE BITS
PE
CS
CLK
TCSL
DI
1
1
1
1 •••
1
1
1
1
8 BITS OF "1"
TRI-STATE
DO
A PREN cycle must immediately precede a PRCLEAR cycle.
FIGURE 2-12: PRWRITE TIMING
PRE
PE
CS
CLK
TCSL
BUSY
TWC
READY
DI
1
0
1
A7 • • •
A0
DO
BUSY
TWC
Protect Register MUST be cleared before a PRWRITE cycle.
A PREN cycle must immediately precede a PRWRITE cycle.
Address bit A7 is a "don't care" for 93LCS56.
READY
© 1996 Microchip Technology Inc.
Preliminary
DS11181D-page 9