24AA1025_13 Datasheet, PDF (9/28 Pages) Microchip Technology – 1024K I2C Serial EEPROM

24AA1025/24LC1025/24FC1025
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start condition from the master, the
control code (four bits), the block select (one bit), the
Chip Select (two bits), and the R/W bit (which is a logic
low) are clocked onto the bus by the master transmitter.
This indicates to the addressed slave receiver that the
address high byte will follow after it has generated an
Acknowledge bit during the ninth clock cycle.
Therefore, the next byte transmitted by the master is
the high-order byte of the word address and will be
written into the Address Pointer of the 24XX1025. The
next byte is the Least Significant Address Byte. After
receiving another Acknowledge signal from the
24XX1025, the master device will transmit the data
word to be written into the addressed memory location.
The 24XX1025 acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle and during this time, the 24XX1025 will not
generate Acknowledge signals as long as the control
byte being polled matches the control byte that was
used to initiate the write (Figure 6-1). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command, but no write
cycle will occur, no data will be written and the device
will immediately accept a new command. After a byte
Write command, the internal address counter will point
to the address location following the one that was just
written.
Note:
When doing a write of less than 128 bytes
the data in the rest of the page is
refreshed along with the data bytes being
written. This will force the entire page to
endure a write cycle, for this reason
endurance is specified per page.
6.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX1025 in the same way
as in a byte write. But instead of generating a Stop
condition, the master transmits up to 127 additional
bytes, which are temporarily stored in the on-chip page
buffer and will be written into memory after the master
has transmitted a Stop condition. After receipt of each
word, the seven lower Address Pointer bits are
internally incremented by one. If the master should
transmit more than 128 bytes prior to generating the
Stop condition, the address counter will roll over and
the previously received data will be overwritten. As with
the byte write operation, once the Stop condition is
received, an internal write cycle will begin (Figure 6-2).
If an attempt is made to write to the array with the WP
pin held high, the device will acknowledge the
command, but no write cycle will occur, no data will be
written and the device will immediately accept a new
command.
6.3 Write Protection
The WP pin allows the user to write-protect the entire
array (00000-1FFFF) when the pin is tied to VCC. If tied
to VSS the write protection is disabled. The WP pin is
sampled at the Stop bit for every Write command
(Figure 1-1). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
Note:
Page write operations are limited to writ-
ing bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer
multiples of the page buffer size (or ‘page
size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
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DS20001941L-page 9