PIC12C509A-04I Datasheet, PDF (89/113 Pages) Microchip Technology – 8-Pin, 8-Bit CMOS Microcontrollers

PIC12C5XX
FIGURE 13-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING -
PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A,
PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519
VDD
MCLR
Internal
POR
32
DRT
Timeout
(Note 2)
Internal
RESET
Watchdog
Timer
RESET
I/O pin
(Note 1)
30
32
32
31
34
34
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
2: Runs in MCLR or WDT reset only in XT and LP modes.
TABLE 13-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC12C508A,
PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A,
PIC12LCR509A, PIC12LCE518 and PIC12LCE519
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 13.1
Parameter
No.
Sym Characteristic
Min Typ⁽¹⁾ Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
2000* — — ns VDD = 5 V
31
Twdt Watchdog Timer Time-out Period 9* 18* 30* ms VDD = 5 V (Commercial)
(No Prescaler)
32
TDRT Device Reset Timer Period⁽²⁾
9* 18* 30* ms VDD = 5 V (Commercial)
34
TioZ I/O Hi-impedance from MCLR Low — — 2000* ns
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 2: See Table 13-6.
© 1999 Microchip Technology Inc.
DS40139E-page 89