PL611S-02 Datasheet, PDF (8/20 Pages) PhaseLink Corporation – 1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock

PL611S-02
3.0 FUNCTIONAL DESCRIPTION
PL611s-02 is a highly featured, very flexible, advanced
programmable PLL design for high performance,
low-power, small form-factor applications. The
PL611s-02 accepts a fundamental input crystal of
10 MHz to 50 MHz or reference clock input of 1 MHz to
200 MHz and is capable of producing two outputs up to
200 MHz. This flexible design allows the PL611s-02 to
deliver any PLL generated frequency, F_REF (Crystal or
REF_CLK) frequency or F_REF/(2×P) to CLK0 and/or
CLK1. The following content explains some of the
design features of the PL611s-02.
3.1 PLL Programming
The PLL in the PL611s-02 is fully programmable. The
PLL is equipped with an 8-bit input frequency divider
(R-Counter), and an 11-bit VCO frequency feedback
loop divider (M-Counter). The output of the PLL is
transferred to a 5-bit post VCO divider (P-Counter).
The output frequency is determined by the following
formula:
EQUATION 3-1:
F_OUT
=
-^F----^R---^E---^F-----^-----^M----
RP
3.2 Clock Output (CLK0)
CLK0 is the main clock output. The output of CLK0 can
be configured as the PLL output (F_VCO/(2×P)), F_REF
(Crystal or REF_CLK) output, or F_REF/(2×P) output.
The output drive level can be programmed to Low Drive
(4 mA), Standard Drive (8 mA) or High Drive (16 mA).
The maximum output frequency is determined by the
Power Supply Voltage; 200 MHz at 3.3V, 166 MHz at
2.5V and 110 MHz at 1.8V.
3.3 Clock Output (CLK1)
The CLK1 feature allows the PL611s-02 to have an
additional clock output programmed to one of the
following:
• F_REF - Reference (Crystal or REF_CLK)
Frequency
• F_REF / 2
• CLK0
• CLK0 / 2
3.4 Maximum VCO Frequency
For the best performance, we recommend to use the
highest VCO frequency allowed at the power supply
voltage where the PL611s-02 will be used. It is actually
the maximum VCO frequency that determines the
maximum output frequency. When a PL611s-02 is
programmed for use at a certain power supply voltage,
DS20005670A-page 8
it is safe to use that part at higher voltages also
because at higher voltages the maximum VCO
frequency is also higher. The other way around, using
the part at a lower voltage than what it was originally
configured for, is not safe.
3.5 Output Enable (OE)
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE pin.
The OE pin incorporates a 60 kΩ pull up resistor giving
a default condition of logic “1”.
3.6 Power-Down Control (PDB)
The Power Down (PDB) feature allows the user to put
the PL611s-02 into “Sleep Mode”. When activated
(logic ‘0’), PDB disables the PLL, the oscillator circuitry,
counters, and all other active circuitry. In Power Down
mode the IC consumes <10 μA of power. The PDB pin
incorporates a 60 kΩ pull up resistor giving a default
condition of logic “1”.
3.7 Frequency Select (FSEL)
The Frequency Select (FSEL) feature allows the
PL611s-02 to switch between two pre-programmed
outputs allowing the device “On the Fly” frequency
switching. The FSEL pin incorporates a 60 kΩ pull up
resistor giving a default condition of logic “1”.
 2016 Microchip Technology Inc.