PL610-01 Datasheet, PDF (8/20 Pages) PhaseLink Corporation – 1.8V to 3.3V, 1MHz to 130MHz XO IC

PL610-01
4.0 LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a
performance-optimized PCB design.
4.1 Signal Integrity and Termination
Considerations
• Keep traces short.
• Trace = Inductor. With a capacitive load this
creates ringing.
• Long trace = Transmission Line. Without proper
termination this will cause reflections (looks like
ringing).
• Design long traces as “striplines” or “microstrips”
with defined impedance.
• Match trace at one side to avoid reflections
bouncing back and forth.
4.2 Decoupling and Power Supply
Considerations
• Place decoupling capacitors as close as possible
to the V_DD pin(s) to limit noise from the power
supply.
• Multiple V_DD pins should be decoupled separately
for best performance.
• Addition of a ferrite bead in series with V_DD can
help prevent noise from other board sources.
• Value of decoupling capacitor is frequency
dependent. Typical values to use are 0.1 µF for
designs using crystals <50 MHz and 0.01 µF for
designs using crystals >50 MHz.
4.3 Typical CMOS Termination
Place series resistor as close as possible to the CMOS output.
CMOS Output Buffer
(Typical buffer impedance 20:
50: line
To CMOS Input
Series Resistor
Use value to match output
buffer impedance to 50:
trace. Typical value 30:
FIGURE 4-1:
Typical CMOS Termination.
4.4 Crystal Tuning Circuit
Series and parallel capacitors are used to fine tune the crystal load to the circuit load.
Cst
XIN
Cpt
XOUT
Cpt
CST: Series capacitor, used to lower circuit load to match crystal load. Raises frequency offset. This can be eliminated
by using a crystal with a C_LOAD of equal or greater value than the oscillator.
CPT: Parallel capacitors, used to raise the circuit load to match the crystal load. Lowers frequency offset.
DS20005615A-page 8
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