PL610-01 Datasheet, PDF (7/20 Pages) PhaseLink Corporation – 1.8V to 3.3V, 1MHz to 130MHz XO IC

3.0 FUNCTIONAL DESCRIPTION
PL610-01 is a highly featured, very flexible, advanced
XO design for high performance, low-power, small
form-factor applications. The PL610-01 accepts a
fundamental input crystal of 5 MHz to 130 MHz or a
reference clock input of 1 MHz to 130 MHz and is
capable of producing two outputs up to 130 MHz. This
flexible design allows the PL610-01 to deliver any
frequency, F_REF (Crystal or Ref Clk) frequency, F_REF/2
or F_REF/P to CLK0 and/or CLK1. Some of the design
features of the PL610-01 are mentioned below.
3.1 Clock Output (CLK0)
CLK0 is the main clock output. The output from CLK0
can be F_REF (Crystal or Ref Clk), F_REF/2 or F_REF/P
output. The output drive level can be programmed to
Low Drive (4 mA), Standard Drive (8 mA), or High Drive
(16 mA).
3.2 Programmable I/O (OE/PDB/CLK1)
The PL610-01 provides one programmable I/O pin
which can be configured as one of the following
functions:
3.2.1 OUTPUT ENABLE (OE)
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE pin.
The OE pin incorporates a 60 kΩ pull-up resistor giving
a default condition of logic “1”.
3.2.2 POWER DOWN CONTROL (PDB)
The Power Down (PDB) feature allows the user to put
the PL610-01 into “Sleep Mode.” When activated (logic
‘0’), PDB disables the PLL, the oscillator circuitry,
counters, and all other active circuitry. In Power Down
mode the IC consumes <10 µA of power. The PDB pin
incorporates a 10 MΩ pull-up resistor giving a default
condition of logic “1”.
3.2.3 CLOCK OUTPUT (CLK1)
The CLK1 feature allows the PL610-01 to have an
additional clock output programmed to one of the
following:
• F_REF - Reference (Crystal or Ref Clk) Frequency
• F_REF/2
• CLK0
 2016 Microchip Technology Inc.
PL610-01
DS20005615A-page 7