EQCO875SC.3 Datasheet, PDF (8/20 Pages) Microchip Technology – EQCO875SC.3/EQCO850SC.3 Single-Coax Transceiver for Fast Ethernet

EQCO875SC.3/EQCO850SC.3
3.1 Guidelines for PCB Layout
Because signals are strongly attenuated by long cables,
special attention must be paid on the PCB layout
between the coaxial connector and the EQCO875SC.3.
The EQCO875SC.3 should be placed as close as is
practical to the coaxial connector. The trace between
the coaxial connector and the SDIO pin of the
EQCO875SC.3 must be a 75Ω (50Ω for
EQCO850SC.3) trace referenced to GND. To avoid
noise pickup, other traces carrying digital signals or
fast-switching signals should be placed as far away as
possible from this trace.
The ground layout on the EQCO875SC.3 is crucial to
the EMC and EMI performance of the circuit. The
AGND connection should be connected directly to the
body of the connector as shown. Similarly, AVCC
FIGURE 3-2:
TYPICAL PCB LAYOUT
should be decoupled directly to the connector body
(see the position of C9). The termination resistor (R1
in Figure 3-1 and Figure 3-2) must have its ground
connection at the connector body. The impedance of
all the traces must be well controlled, including on the
connector itself. To compensate for parasitic
capacitances, the ground and power planes
underneath L1 and part of the coax connector need to
be removed, as indicated by the green areas on
Figure 3-2.
The SDIp/SDIn and SDOp/SDOn differential traces
should be laid out as 100Ω differential traces.
The following diagram shows the layout of the critical
section of the PCB corresponding to the circuit of
Figure 3-1 from the coax connector to the twin
differential pairs:
DS60001314A-page 8
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