EQCO875SC.3 Datasheet, PDF (5/20 Pages) Microchip Technology – EQCO875SC.3/EQCO850SC.3 Single-Coax Transceiver for Fast Ethernet

EQCO875SC.3/EQCO850SC.3
FIGURE 1-3:
EQCO875SC.3 BLOCK DIAGRAM SHOWING ELECTRICAL CONNECTIONS
EQCO875SC.3
SDIp
SDIn
Input
Pre-Driver
Active Signal
Splitter/Combiner
SDIO
REF
Transmit
Wake-Up
Detection
Equalizer
Core
SDOp
SDOn
RX Output
Driver
1.1 SDIp/SDIn
SDIp/SDIn together form a differential input pair. The
serial data received on these pins will be transmitted on
SDIO. The Input Pre-Driver automatically corrects for
variations in signal levels and different edge slew rates at
these inputs before they go into the Active Splitter/
Combiner for transmission over the coax.
Both SDIp and SDIn inputs are differentially terminated by
110Ω on-chip. The center of the 110Ω is connected to
DGND with a 10 kΩ resistor for DC biasing. The inputs
also have protection diodes to ground for ESD purposes.
These inputs should always be capacitively coupled to the
FX output of the Ethernet PHY. A Transmit Wake-Up
detection circuit puts both the Input Pre-Driver and the
Active Signal Splitter/Combiner into a low-power mode
when no signal is detected on the SDIp/SDIn signal pair.
1.2 SDIO/REF
The signal on the SDIO pin is the sum of the incoming
signal (i.e. the signal transmitted by the EQCO875SC on
the far-end side of the coax) and the outgoing signal (i.e.
the signal created based on SDIp/SDIn). The far-end
signal is extracted by subtraction of the near-end signal,
and it is this voltage that the equalizer analyses and
adaptively equalizes for level and frequency response
based on the knowledge that the originating signal is 4B/
5B encoded before transmission.
The REF signal carries a precise anti-phase current to the
transmit current on SDIO. REF must be connected
directly to AGND at the connector (see Figure 3-2) via a
resistor precisely matched to the impedance of the
coaxial cable used.
 2009-2016 Microchip Technology Inc.
1.3 SDOp/SDOn
SDOp/SDOn together form a differential pair outputting
the reconstructed far-end transmit signal. The
EQCO850SC-HS uses LVDS drivers with source
matching for a 100Ω transmission line. This LVDS
signal can normally be connected (subject to input
common-mode requirements) directly to the RX signal
pair of a standard LVDS receiver.
1.4 OPT0, OPT1
Connect Opt0 to DGND and Opt1 to DVCC to enable
Fast Ethernet mode.
1.5 CLK, DAT Pins
These pins are normally used to access an internal
register during production test. Connect them to DGND
for normal operation. They should not be left floating.
DS60001314A-page 5