93AA46 Datasheet, PDF (8/12 Pages) Microchip Technology – 1K/2K/4K 1.8V Microwire Serial EEPROM

93AA46/56/66
3.0 PIN DESCRIPTION
3.1 Chip Select (CS)
A HIGH level selects the device. A LOW level deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought LOW during a program cycle,
the device will go into standby mode as soon as the pro-
gramming cycle is completed.
CS must be LOW for 250 ns minimum (TCSL) between
consecutive instructions. If CS is LOW, the internal con-
trol logic is held in a RESET status.
3.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93AAXX.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be continued
anytime with respect to clock HIGH time (TCKH) and
clock LOW time (TCKL). This gives the controlling mas-
ter freedom in preparing opcode, address, and data.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a start condition the specified number
of clock cycles (respectively LOW to HIGH transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (see instruc-
tion set truth table). CLK and DI then become don't care
inputs waiting for a new start condition to be detected.
Note: CS must go LOW between consecutive
instructions.
3.3 Data In (DI)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
3.4 Data Out (DO)
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (TPD after the positive
edge of CLK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY sta-
tus information is available on the DO pin if CS is
brought HIGH after being LOW for minimum chip select
LOW time (TCSL) and an ERASE or WRITE operation
has been initiated.
The status signal is not available on DO, if CS is held
LOW or HIGH during the entire WRITE or ERASE
cycle. In all other cases DO is in the HIGH-Z mode. If
status is checked after the WRITE/ERASE cycle, a pull-
up resistor on DO is required to read the READY signal.
3.5 Organization (ORG)
When ORG is connected to VCC, the (x16) memory
organization is selected. When ORG is tied to VSS, the
(x8) memory organization is selected. ORG can only be
floated for clock speeds of 1MHz or less for the (x16)
memory organization. For clock speeds greater than 1
MHz, ORG must be tied to VCC or VSS.
DS20067G-page 8
© 1996 Microchip Technology Inc.