93AA46 Datasheet, PDF (5/12 Pages) Microchip Technology – 1K/2K/4K 1.8V Microwire Serial EEPROM

2.8 Erase All (ERAL)
The ERAL instruction will erase the entire memory
array to the logical “1” state. The ERAL cycle is identical
to the ERASE cycle except for the different opcode. The
ERAL cycle is completely self-timed and commences at
the falling edge of the CS. Clocking of the CLK pin is not
necessary after the device has entered the self clocking
mode. The ERAL instruction is guaranteed at 5V ±
10%.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire write cycle is complete.
The ERAL cycle takes (8 ms typical).
FIGURE 2-1: SYNCHRONOUS DATA TIMING
V IH
CS
V IL
TCSS
V IH
CLK
V IL
V IH
DI
V IL
TDIS
DO ^VOH
(READ) _VOL
TSV
DO ^VOH
(PROGRAM)
V OL
TCKH
TDIH
TPD
FIGURE 2-2: READ TIMING
CS
CLK
93AA46/56/66
2.9 Write All (WRAL)
The WRAL instruction will write the entire memory array
with the data specified in the command. The WRAL
cycle is completely self-timed and commences at the
falling edge of the CS. Clocking of the CLK pin is not
necessary after the device has entered the self clocking
mode. The WRAL command does include an auto-
matic ERAL cycle for the device. Therefore, the WRAL
instruction does not require an ERAL instruction but the
chip must be in the EWEN status. The WRAL instruc-
tion is guaranteed at 5V ± 10%.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
The WRAL cycle takes 16 ms typical.
TCKL
TCSH
TPD
STATUS VALID
TCZ
TCZ
TCSL
DI
11
0 • An • • • A0
DO
T_TR_RII_--_SS_TT_AA_TT_EE_™^®
0
Dx • • • D0 Dx* • • • D0 Dx* • • • D0
Tri-State is a registered trademark of National Semiconductor Incorporated.
© 1996 Microchip Technology Inc.
DS20067G-page 5