24C32A Datasheet, PDF (8/12 Pages) Microchip Technology – 32K 5.0V I 2 C O Serial EEPROM

24C32A
6.3 Contiguous Addressing Across
Multiple Devices
The device select bits A2, A1, A0 can be used to
expand the contiguous address space for up to 256K
bits by adding up to eight 24C32A's on the same bus.
In this case, software can use A0 of the control byte as
address bit A12, A1 as address bit A13, and A2 as
address bit A14.
6.4 Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24C32A transmits the
first data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24C32A to transmit the
next sequentially addressed 8-bit word (Figure 6-3).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge but will gen-
erate a stop condition.
To provide sequential reads the 24C32A contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation. The internal address pointer will
automatically roll over from address 0FFF to address
000 if the master acknowledges the byte received from
the array address 0FFF.
FIGURE 6-2: RANDOM READ
S
T
BUS ACTIVITY _A
MASTER
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
S
T
ADDRESS ^A
LOW BYTE ^R
T
CONTROL
BYTE
S
DATA
T
BYTE
O
P
SDA LINE
0000
BUS ACTIVITY
A
A
A
C
C
C
K
K
K
A
N
C
O
K
A
C
K
FIGURE 6-3: SEQUENTIAL READ
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
SDA LINE
A
A
A
A
C
C
C
C
BUS ACTIVITY
K
K
K
K
S
T
DATA n + x O
P
N
O
A
C
K
DS21163B-page 8
Preliminary
© 1996 Microchip Technology Inc.