24C32A Datasheet, PDF (6/12 Pages) Microchip Technology – 32K 5.0V I 2 C O Serial EEPROM

24C32A
4.0 WRITE OPERATION
4.1 Byte Write
Following the start condition from the master, the con-
trol code (four bits), the device select (three bits), and
the R/W bit which is a logic low are clocked onto the bus
by the master transmitter. This indicates to the
addressed slave receiver that a byte with a word
address will follow after it has generated an acknowl-
edge bit during the ninth clock cycle. Therefore, the next
byte transmitted by the master is the high-order byte of
the word address and will be written into the address
pointer of the 24C32A. The next byte is the least signif-
icant address byte. After receiving another acknowl-
edge signal from the 24C32A the master device will
transmit the data word to be written into the addressed
memory location.
The 24C32A acknowledges again and the master gen-
erates a stop condition. This initiates the internal write
cycle, and during this time the 24C32A will not generate
acknowledge signals (Figure 4-1).
4.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24C32A in the same way as
in a byte write. But instead of generating a stop condi-
tion, the master transmits up to 32 bytes which are tem-
porarily stored in the on-chip page buffer and will be
written into memory after the master has transmitted a
stop condition. After receipt of each word, the five lower
address pointer bits are internally incremented by one.
If the master should transmit more than 32 bytes prior
to generating the stop condition, the address counter
will roll over and the previously received data will be
overwritten. As with the byte write operation, once the
stop condition is received, an internal write cycle will
begin. (Figure 4-2).
FIGURE 4-1: BYTE WRITE
BUS ACTIVITY
MASTER
S
T
A CONTROL
R BYTE
T
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
S
T
DATA
O
P
SDA LINE
0000
BUS ACTIVITY
A
A
A
A
C
C
C
C
K
K
K
K
FIGURE 4-2: PAGE WRITE
S
BUS ACTIVITY
MASTER
T
A
R
T
SDA LINE
BUS ACTIVITY
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
DATA BYTE 0
0000
A
A
A
C
C
C
K
K
K
S
T
DATA BYTE 31
O
P
A
C
K
DS21163B-page 6
Preliminary
© 1996 Microchip Technology Inc.