PIC16C717_13 Datasheet, PDF (77/224 Pages) Microchip Technology – 18/20-Pin, 8-Bit CMOS Microcontrollers with 10/12-Bit A/D

For more information about these SSP modes see Sec-
tion 15 of the PIC Mid-Range MCU Family Reference
Manual (DS33023).
9.2.2 SLAVE MODE
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse.
Then, it loads the SSPBUF register with the received
value currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module to generate a NACK pulse in lieu of
the ACK pulse:
a) The buffer full bit BF (SSPSTAT<0>) is set
before the transfer is received.
b) The overflow bit SSPOV (SSPCON<6>) is set
before the transfer is received.
If the BF bit is set, the SSPSR register value is not
loaded into the SSPBUF. However, both the SSPIF and
SSPOV bits are set. Table 9-2 shows what happens
when a data transfer byte is received, given the status
of bits BF and SSPOV. The shaded cells show the con-
dition where user software did not properly clear the
overflow condition. The BF flag bit is cleared by reading
the SSPBUF register. The SSPOV flag bit is cleared
through software.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times
of the I²C specification as well as the requirements of
the MSSP module are shown in timing parameters
#100 and #101 of the Electrical Specifications.
9.2.2.1 7-BIT ADDRESSING
Once the MSSP module has been enabled
(SSPEN=1), the slave module waits for a START con-
dition to occur. Following the START condition, eight
bits are shifted into the SSPSR register. All incoming
bits are sampled on the rising edge of the clock (SCL)
line. The received address (register SSPSR<7:1>) is
compared to the stored address (register
SSPADD<7:1>). SSPSR<0> is the R/W bit and is not
considered in the comparison. Comparison is made on
the falling edge of the eighth clock (SCL) pulse. If the
addresses match, and the BF and SSPOV bits are
clear, the following events occur:
a) The SSPSR register value is transferred to the
SSPBUF register on the falling edge of the
eighth SCL pulse.
b) The buffer full bit; BF is set on the falling edge of
the eighth SCL pulse.
c) An ACK pulse is generated during the ninth
clock cycle.
d) SSP interrupt flag bit; SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
PIC16C717/770/771
9.2.2.2 10-BIT ADDRESSING
In 10-bit mode, the basic receive and transmit opera-
tions are the same as in the 7-bit mode. However, the
criteria for address match are more complex.
Two address bytes need to be received by the slave.
The five Most Significant bits (MSbs) of the first
address byte specify that this is a 10-bit address. The
LSb of the first received address byte is the R/W bit,
which must be zero, specifying a write so the slave
device will receive the second address byte. For a 10-
bit address, the first byte equals ‘11110 A9 A8 0’,
where A9 and A8 are the two MSbs of the address. The
sequence of events for a 10-bit address is as follows,
with steps 7 through 9 applicable only to the slave-
transmitter:
1. Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
5. Update the SSPADD register with the first (high)
byte of Address. This will clear bit UA and
release the SCL line.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated START condition.
8. Receive first (high) byte of Address with R/W bit
set to 1 (bits SSPIF and BF are set). This also
puts the MSSP module in the Slave-transmit
mode.
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Note:
Following the Repeated START condition
(step 7) in 10-bit mode, the user only
needs to match the first 7-bit address. The
user does not update the SSPADD for the
second half of the address.
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Advance Information
DS41120C-page 77