PIC12F683 Datasheet, PDF (73/148 Pages) Microchip Technology – 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC12F683
11.2 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the GP2/AN2/T0CKI/INT/
COUT/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits, CCP1M<3:0> (CCP1CON<3:0>). At the same
time, interrupt flag bit, CCP1IF (PIR1<5>), is set.
FIGURE 11-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CCP1CON<3:0>
Mode Select
GP2/CCP1
pin
Set Flag bit CCP1IF
(PIR1<5>)
CCPR1H CCPR1L
Q S _Output
Logic
R
Match
Comparator
TRISIO<2>
Output Enable
TMR1H TMR1L
Special Event Trigger
Special Event Trigger will:
• Clear TMR1H and TMR1L registers
• NOT set interrupt flag bit TMR1F (PIR1<0>)
• Set the GO/DONE bit (ADCON0<1>)
11.2.1 CCP1 PIN CONFIGURATION
The user must configure the GP2/AN2/T0CKI/INT/
COUT/CCP1 pin as an output by clearing the
TRISIO<2> bit.
Note:
Clearing the CCP1CON register will
force the GP2/AN2/T0CKI/INT/COUT/
CCP1 compare output latch to the default
low level. This is not the GPIO data latch.
11.2.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
11.2.3 SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1 pin is not affected.
The CCP1IF (PIR1<5>) bit is set, causing a CCP
interrupt (if enabled). See Register 11-1.
11.2.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair and starts A/D conversion, if
enabled. This allows the CCPR1 register to effectively
be a 16-bit programmable period register for Timer1.
Note:
The special event trigger from the CCP1
modules will not set interrupt flag bit
TMR1IF (PIR1<0>).
TABLE 11-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Addr Name Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 Bit 1
Bit 0
Value on
POR, BOD
Value on
all other
Resets
0Bh/
8Bh
0Ch
0Eh
0Fh
INTCON
PIR1
TMR1L
TMR1H
GIE
PEIE
T0IE
INTE
GPIE
T0IF INTF GPIF 0000 0000 0000 0000
EEIF ADIF CCP1IF
—
CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
1Ah CMCON1 —
—
—
—
—
— T1GSS CMSYNC ---- --10 ---- --10
13h CCPR1L Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx uuuu uuuu
14h CCPR1H Capture/Compare/PWM Register 1 High Byte
xxxx xxxx uuuu uuuu
15h CCP1CON —
—
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
8Ch PIE1
EEIE ADIE CCP1IE
—
CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000
Legend: — = unimplemented locations, read as ‘0’, u = unchanged, x = unknown.
Shaded cells are not used by the Capture, Compare or Timer1 module.
 2004 Microchip Technology Inc.
Preliminary
DS41211B-page 71