EQCO850SC.3-HS Datasheet, PDF (7/24 Pages) Microchip Technology – Pb-Free and RoHS Compliant

EQCO850SC.3-HS/EQCO875SC.3-HS
3.0 APPLICATION INFORMATION
Figure 3-1 illustrates a typical schematic implementation.
FIGURE 3-1:
EQCO850SC.3-HS TYPICAL APPLICATION CIRCUIT
3V3
100Ω
Differential
traces
Ferrite
bead
LVDS
TX
LVDS
RX
0.1uF
0.1uF
VCC
SDIp
AVCC
SDIn
0.1uF
GND
SDOp
SDIO
REF
SDOn AGND
10nF
10nF
10nF
Coax
Connector
50Ω
1%
50Ω
traces ^GND
GND
Note: For EQCO875SC.3-HS, replace the two 50Ω references with two 75Ω references.
To improve isolation from noise on the board power
plane and improve EMC immunity and emissions, it is
recommended to power the transmit side of the
equalizer (AVCC) through a ferrite bead. A 0.1 µF
decoupling capacitor should be placed as close as
possible to the chip between the VCC pin and the GND
pin. Ground vias should be placed as close as possible
to the device GND pins to minimize inductance.
In full duplex, the maximum-length performance
depends on the level of near-end crosstalk and far-end
return-loss. For full-duplex operation, position the chip
close to the used connector.
All the elements need to have impedances according to
the choice between a 50Ω system or a 75Ω system: the
chips used on both sides, the impedances between the
chip and the connector, the PCB connector itself, the
connectors on the coax cable and the coax itself. If one
impedance is wrong (e.g. a 75Ω BNC connector in a
50Ω system), this impedance discontinuity will cause a
reflection, limiting the performance of the full-duplex
maximum cable length.
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DS60001313A-page 7