24FC32 Datasheet, PDF (7/12 Pages) Microchip Technology – 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM

5.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a start condition followed by the control byte for
a write command (R/W = 0). If the device is still busy
with the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.
FIGURE 5-1: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
No
Acknowledge
(ACK = 0)?
Yes
Next
Operation
24FC32
6.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
6.1 Current Address Read
The 24FC32 contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address n (n is any legal address), the next current
address read operation would access data from
address n + 1. Upon receipt of the slave address with
R/W bit set to one, the 24FC32 issues an acknowledge
and transmits the eight bit data word. The master will
not acknowledge the transfer but does generate a stop
condition and the 24FC32 discontinues transmission
(Figure 6-1).
6.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24FC32 as part of a write operation (R/W bit set to 0).
After the word address is sent, the master generates a
start condition following the acknowledge. This
terminates the write operation, but not before the
internal address pointer is set. Then the master issues
the control byte again but with the R/W bit set to a one.
The 24FC32 will then issue an acknowledge and
transmit the eight bit data word. The master will not
acknowledge the transfer but does generate a stop con-
dition which causes the 24FC32 to discontinue trans-
mission (Figure 6-2).
FIGURE 6-1:
CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
S
T
A _CONTROL
R
BYTE
T
S
T
DATA n
O
P
SDA LINE
BUS ACTIVITY
A
N
C
O
K
A
C
K
© 1996 Microchip Technology Inc.
DS21126B-page 3-7